Senior ASIC Design Engineer: Imaging Pipelines

Amazon Lab126; Sunnyvale (CA); On-site; USD 143,300 - 247,600; Full time

Benefits offered by this job

Competitive salary

Equity and sign-on bonuses

Workplace accommodations for applicants with disabilities

Job summary

A leading technology company is seeking a Senior ASIC Design Engineer for their Hardware Compute Group in Sunnyvale, California. This role involves architecting and designing advanced imaging hardware while collaborating across various disciplines. Candidates should have a Master’s or Ph.D. in Electrical Engineering, with substantial experience in RTL development and Image Signal Processing pipelines. Competitive pay ranges from $143,300 to $247,600 annually based on experience and location, along with other compensation benefits.

Qualifications

• 5+ years of RTL development experience with a proven tape-out production silicon track record.
• Proficiency in designing Image Signal Processing pipelines.
• Strong skills in Verilog/SystemVerilog with bench experience.

Responsibilities

• Architect and design imaging hardware.
• Collaborate across multiple disciplines to finalize designs.
• Develop design specifications and documentation.

Skills

RTL development

Image Signal Processing (ISP)

Verilog/SystemVerilog

performance/power/area analysis

design methodologies and EDA tools

C/C++ programming

Python, Tcl, Perl scripting

Education

Master’s degree or Ph.D. in Electrical Engineering

Job description

A leading technology company is seeking a Senior ASIC Design Engineer for their Hardware Compute Group in Sunnyvale, California. This role involves architecting and designing advanced imaging hardware while collaborating across various disciplines. Candidates should have a Master’s or Ph.D. in Electrical Engineering, with substantial experience in RTL development and Image Signal Processing pipelines. Competitive pay ranges from $143,300 to $247,600 annually based on experience and location, along with other compensation benefits.