Senior ASIC Design Engineer – Co-Packaged Optics

Ayar Labs; San Jose (CA); On-site; USD 180,000 - 223,000; Full time

Job summary

A cutting-edge technology company in San Jose is seeking an ASIC Sr. Staff Engineer responsible for the design and debug of complex digital subsystems. The ideal candidate will have a BS or MS in Electrical Engineering and over 5 years of experience in ASIC design and verification. Proficiency in Verilog, SystemVerilog, and Python is essential. This role offers an opportunity to work in a fast-paced startup environment with competitive remuneration ranging from $180,000 to $223,000.

Qualifications

• 5+ years of work or academic experience in ASIC design.
• History of assuming responsibility for a variety of technical tasks.
• Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB).

Responsibilities

• Develop detailed digital algorithm specifications.
• Develop and optimize RTL in Verilog for ASICs.
• Bring up, evaluate, and debug in-house custom silicon.

Skills

Verilog

SystemVerilog

Python

ASIC verification tools

Digital timing constraints

Digital design experience

SOC interconnect fabrics

Education

BS or MS in Electrical Engineering

Tools

XCelium

VCS

Questa

Genus

Design Compiler

Job description

A cutting-edge technology company in San Jose is seeking an ASIC Sr. Staff Engineer responsible for the design and debug of complex digital subsystems. The ideal candidate will have a BS or MS in Electrical Engineering and over 5 years of experience in ASIC design and verification. Proficiency in Verilog, SystemVerilog, and Python is essential. This role offers an opportunity to work in a fast-paced startup environment with competitive remuneration ranging from $180,000 to $223,000.