Senior ASIC Design Engineer – Networking Hardware

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 120,000 - 243,000; Full time

Benefits offered by this job

Health & Wellbeing

Career Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA, is seeking an ASIC Design Engineer for an onsite role. You will design high-speed ASICs for networking, starting from specifications and delivering RTL in Verilog/SystemVerilog.

Collaborate with Physical Design and Verification teams, write coverage, and mentor new graduates. A BS in Electrical Engineering with 4+ years of relevant experience is required, MS preferred.

Qualifications

• BS in Electrical Engineering required; MS preferred.
• 4+ years of relevant ASIC design experience.
• Strong knowledge of Verilog/SystemVerilog.
• Familiarity with computer architecture and networking protocols.

Responsibilities

• You will start with a functional spec and create micro-architectural specs meeting power/area goals.
• Implement design using Verilog/SystemVerilog.
• Write functional coverage and SVA for verification.
• Collaborate with Physical Design for floorplanning and timing closure.
• Assist verification team and mentor new graduates.

Skills

ASIC design

Verilog/SystemVerilog

Computer Architecture

C/C++

Python/Perl

Education

Bachelor’s degree in Electrical Engineering

Master’s degree preferred

Tools

EDA tools

Synthesis tools

Job description

Hewlett Packard Enterprise in Sunnyvale, CA, is seeking an ASIC Design Engineer for an onsite role. You will design high-speed ASICs for networking, starting from specifications and delivering RTL in Verilog/SystemVerilog.

Collaborate with Physical Design and Verification teams, write coverage, and mentor new graduates. A BS in Electrical Engineering with 4+ years of relevant experience is required, MS preferred.