Senior ASIC Design Engineer, Embedded Printer ICs

HP; Vancouver (WA); On-site; USD 116,000 - 182,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Long term disability insurance

Employee assistance program

Flexible spending account

Life insurance

Generous paid parental leave

Job summary

HP is seeking an experienced Senior ASIC/SoC Design Engineer in Vancouver, WA to lead blocks of digital ASICs from design to silicon verification. You will partner with internal and external teams to align on specifications, drive reviews, and advance RA roadmaps for inkjet and laserjet architectures.

Candidates should have a BS/MS in EE and 8–10 years in ASIC/SOC design, with deep knowledge of submicron tech, RTL-to-silicon flows, and strong EDA tool proficiency. Relocation offered.

Qualifications

• BS or MS degree in electrical engineering with focus on VLSI design.
• 8–10 years of ASIC or SOC design and development experience.

Responsibilities

• Lead blocks or subsystems of digital ASICs from design to silicon verification.
• Collaborate with partners to align on specs and drive reviews.
• Manage relationships with internal and external development partners.
• Contribute to ASIC roadmaps and future innovations.
• Lead cross-discipline tasks to triage HW & FW integration issues.
• Support pre-silicon firmware development and verification with FPGA prototyping.

Skills

Submicron technology

Embedded system design

RTL to silicon flow

Verilog/VHDL/SV

Python/C++ scripting

Git/SVN version control

Education

BS or MS in Electrical Engineering

8–10 years ASIC/SOC design experience

Tools

Synopsys EDA tools

Cadence EDA tools

Job description

HP is seeking an experienced Senior ASIC/SoC Design Engineer in Vancouver, WA to lead blocks of digital ASICs from design to silicon verification. You will partner with internal and external teams to align on specifications, drive reviews, and advance RA roadmaps for inkjet and laserjet architectures.

Candidates should have a BS/MS in EE and 8–10 years in ASIC/SOC design, with deep knowledge of submicron tech, RTL-to-silicon flows, and strong EDA tool proficiency. Relocation offered.