Senior ASIC Design Engineer — Co-Packaged Optics

Ayar Labs; San Jose (CA); On-site; USD 180,000 - 223,000; Full time

Job summary

Ayar Labs in San Jose, CA, is seeking an ASIC Senior Staff Engineer to design, bring up, and debug complex digital subsystems in an electro-optical SoC. You will join a small IC design team and contribute across a broad range of tasks while growing with the company.

The ideal candidate will craft specifications from colleagues and customers, develop RTL in Verilog, build testbenches, and document designs to enable backend timing signoff. Self-motivated, independent work is essential.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of work or academic experience in ASIC design.
• Mastery of Verilog and SystemVerilog for RTL design and verification.
• Proficient in ASIC verification tools (XCelium, VCS, Questa).
• Proficient in C/C++, Python.
• Working knowledge of digital timing constraints and ASIC tool flows.
• Experience with multiple clock domains and clock dividers.
• Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB).

Responsibilities

• Develop detailed digital algorithm specifications with cross-domain teams.
• Develop and optimize RTL in Verilog for electro-optical ASICs.
• Create models and testbenches for digital and mixed-signal blocks.
• Document designs for backend ASIC engineers for timing signoff.
• Bringup, evaluation, and debugging of in-house silicon using Python and firmware.
• Contribute to automated design methodologies and flows for ASIC design.
• Work with high-speed interconnects and optical systems.

Skills

Verilog

SystemVerilog

C

C++

Python

ASIC verification tools

Digital timing constraints

Clock domains

AMBA AXI/AHB/APB

Education

BS in Electrical Engineering or Computer Engineering

MS in Electrical / Computer Engineering (preferred)

Tools

XCelium

VCS

Questa

Genus

Design Compiler

Job description

Ayar Labs in San Jose, CA, is seeking an ASIC Senior Staff Engineer to design, bring up, and debug complex digital subsystems in an electro-optical SoC. You will join a small IC design team and contribute across a broad range of tasks while growing with the company.

The ideal candidate will craft specifications from colleagues and customers, develop RTL in Verilog, build testbenches, and document designs to enable backend timing signoff. Self-motivated, independent work is essential.