Senior ASIC Design Engineer

Anysilicon; Santa Clara (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

NVIDIA in Santa Clara, California is seeking an experienced ASIC Design Engineer to contribute to cutting-edge SoCs and GPUs. You will own micro-architecture, implement RTL, and deliver verified, synthesis-timing clean designs for high-performance graphics and AI applications.

Collaborate with architects, designers and verification teams to achieve project goals, making architectural trade-offs based on features, performance and system limits, and ensuring robust debugging and teamwork

Qualifications

• Master's degree or equivalent experience in Electrical/Computer Engineering.
• 8+ years of experience in ASIC design and development.
• Experience in micro-architecture and RTL development in Verilog.
• Familiarity with digital systems, VLSI design, computer architecture, and CMOS circuits.

Responsibilities

• Implement GPU sub-system modules as part of the Design team.
• Make architectural trade-offs based on features, performance, and system limitations.
• Own micro-architecture, implement RTL, and deliver a verified, synthesis/timing clean design.
• Collaborate with architects, designers, and verification teams to achieve project goals.

Skills

Team collaboration

Debugging skills

Interpersonal skills

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

Verilog

Python

C/C++

PCIe/CXL

Job description

Job Description:

NVIDIA is looking for experienced ASIC Design Engineers to contribute to the design and implementation of cutting-edge SoCs and GPUs. This role offers the chance to make a significant impact in a technology-driven environment, influencing a range of products from consumer graphics to self-driving vehicles and AI applications. Join a global team dedicated to pushing the boundaries of computing technology.

Responsibilities:

• Implement GPU sub-system modules as part of the Design team.
• Make architectural trade-offs based on features, performance, and system limitations.
• Own micro-architecture, implement RTL, and deliver a verified, synthesis/timing clean design.
• Collaborate with architects, designers, and verification teams to achieve project goals.

Qualifications:

• Master's Degree in Electrical Engineering or Computer Engineering or equivalent experience.
• 8+ years of experience in ASIC design and development.
• Experience in micro-architecture and RTL development in Verilog.
• Familiarity with digital systems, VLSI design, computer architecture, and CMOS circuits.

Skills:

• Understanding of ASIC design flow including RTL design, verification, and timing analysis.
• Experience with arbiters, scheduling, synchronization, and bus protocols is desirable.
• Knowledge of PCI-Express (Gen 3 and above) or CXL protocol is a plus.
• Proficiency in Python, Perl, and C/C++ programming languages is desirable.
• Strong debugging and analytical skills.
• Excellent interpersonal skills and teamwork abilities.