Senior ASIC CAD Engineer — Synthesis & Power

Palo Alto Networks; Santa Clara (CA); On-site; USD 174,000 - 281,000; Full time

Job summary

Palo Alto Networks is seeking an experienced ASIC CAD Engineer to join our ASIC team in Santa Clara. You will bridge frontend logic and physical design, taking SystemVerilog into synthesis, STA, and power optimization while automating pipelines.

The role requires 10+ years in ASIC front-end design, experience with major EDA tools, and scripting in Perl, Python, and Tcl. You will collaborate with external vendors and maintain design flows to keep tape-out on schedule.

Qualifications

• BS/MS in Electrical/Computer Engineering or CS with 10+ years in ASIC front-end design.
• Proven track record delivering verified netlists to foundries or external ASIC vendors.
• Experience with IP blocks for high-speed interfaces (PCIe, Ethernet, DDR).
• Production experience with major industry tools (Design Compiler/PrimeTime; Genus/Tempus).
• Expert scripting in Perl, Python, Tcl and Linux shells.

Responsibilities

• Drive full-chip and block-level logic synthesis with emphasis on Power, Performance and Area (PPA).
• Formulate timing constraints (SDC) and perform sign-off STA to resolve violations.
• Implement low-power strategies using UPF and analyze dynamic gate-level power.
• Interface with external P&R ASIC vendor; assemble handoff packages and review parasitics for tape-out.
• Develop and enhance Perl, Python and Tcl scripts to automate front-end flows.
• Maintain ASIC CAD infrastructure and design flows to keep the pipeline efficient.

Skills

ASIC front-end design

Timing closure

Power optimization

Scripting: Perl

Scripting: Python

Scripting: Tcl

Linux shell

Education

BS/MS in Electrical/Computer Engineering or Computer Science

Tools

Synopsys Design Compiler/PrimeTime

Cadence Genus/Tempus

Job description

Palo Alto Networks is seeking an experienced ASIC CAD Engineer to join our ASIC team in Santa Clara. You will bridge frontend logic and physical design, taking SystemVerilog into synthesis, STA, and power optimization while automating pipelines.

The role requires 10+ years in ASIC front-end design, experience with major EDA tools, and scripting in Perl, Python, and Tcl. You will collaborate with external vendors and maintain design flows to keep tape-out on schedule.