ASIC Design Engineer - Cache Controller

Apple Inc.; Santa Clara (CA); On-site; USD 184,700 - 324,800; Full time

Job summary

Apple Inc. in Santa Clara, CA, is seeking an experienced hardware design engineer to build the cache subsystem for a high-performance System on a Chip (SoC). The role involves RTL design, micro-architecture development, and performance/power/area trade-off analysis in line with architectural guidelines.

The candidate will collaborate on front-end netlist, timing closure with the physical design team, and contribute to shaping memory hierarchy to meet demanding latency and bandwidth requirements.

Qualifications

• 10+ years of full-time ASIC design experience.
• Memory system development.
• PPA (performance/power/area) analysis.
• Cache design background including an understanding of different memory organizations and tradeoffs.
• Hands on Experience with multi-processor cache coherence protocols.
• B.S. in a relevant field.

Responsibilities

• Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
• Develop cache micro-architecture based on architecture guidelines and model analysis.
• Explore architecture trade-offs in system performance, area, and power consumption.
• Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
• Work on front-end netlist and area/timing analysis of the cache subsystem.
• Work with physical design team on the timing closure of the cache subsystem.

Skills

Memory system development

PPA analysis

Cache design

Cache coherence protocols

Bachelor's degree in a relevant field

Education

Bachelor's degree in a relevant field

Tools

RTL design tools

Job description

Santa Clara, California, United States Hardware

Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.

Description

Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore architecture trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem. Work on front-end netlist and area/timing analysis of the cache subsystem. Work with physical design team on the timing closure of the cache subsystem.

Minimum Qualifications

• 10 + years of full time ASIC design experience
• memory system development
• PPA (performance/power/area) analysis
• Cache design background including an understanding of different memory organizations and tradeoffs.
• Hands on Experience with multi-processor cache coherence protocols
• B.S. in a relevant field

Preferred Qualifications

• Knowledge of high-performance coherent memory systems or interconnect architectures
• Knowledge of high-performance DRAM controller
• M.S in a relevant field.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Learn more about Apple Benefits

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

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Apple accepts applications to this posting on an ongoing basis.