Senior Analog Layout Lead – High-Performance SoCs

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization is seeking an experienced Analog Layout Lead to drive the physical implementation of complex analog and mixed‑signal blocks for custom chips used in VR/AR wearables. You will own full‑custom layout, define physical design methodologies, and partner with circuit design and verification teams to meet power, performance and area targets.

You will lead layout of PLLs, ADCs, DACs, LDOs and high‑speed interfaces, enforce design rules, guide parasitic extraction

Qualifications

• 8+ years of experience in full-custom analog and mixed-signal layout for production silicon.
• 8+ years of hands-on experience with Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification.
• Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out.
• Experience defining and implementing layout methodologies for matching, shielding, and noise isolation in mixed-signal environments.
• Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints and implementation decisions.
• Experience managing and mentoring layout engineers and coordinating work with external contractors.

Responsibilities

• Lead full-custom layout of complex analog and mixed-signal blocks including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon targeting VR and AR wearable platforms.
• Define and enforce analog layout methodologies, design rules, and best practices across the physical design team.
• Drive parasitic‑aware layout strategies to meet stringent noise, matching, and signal integrity requirements for mixed‑signal designs.
• Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results.
• Own physical verification closure including DRC, LVS, and antenna checks across advanced process nodes.
• Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts.
• Provide technical guidance and layout direction to other engineers on the team, reviewing layouts and driving consistency in methodology.
• Partner with process technology and design kit teams to evaluate new process nodes and contribute to PDK qualification for analog layout.
• Identify and resolve layout‑induced performance issues through post‑layout simulation analysis and iterative design refinement.
• Own long‑term physical design roadmaps and methodology investments that scale across multiple silicon programs.
• Manage layout contractors to deliver high‑quality final GDS on schedule and in alignment with design specifications.

Tools

Cadence Virtuoso

Job description

Meta's Silicon Engineering organization is seeking an experienced Analog Layout Lead to drive the physical implementation of complex analog and mixed‑signal blocks for custom chips used in VR/AR wearables. You will own full‑custom layout, define physical design methodologies, and partner with circuit design and verification teams to meet power, performance and area targets.

You will lead layout of PLLs, ADCs, DACs, LDOs and high‑speed interfaces, enforce design rules, guide parasitic extraction