Analog Layout Lead, Silicon Engineering

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization is seeking an experienced Analog Layout Lead to drive the physical implementation of complex analog and mixed‑signal blocks for custom chips used in VR/AR wearables. You will own full‑custom layout, define physical design methodologies, and partner with circuit design and verification teams to meet power, performance and area targets.

You will lead layout of PLLs, ADCs, DACs, LDOs and high‑speed interfaces, enforce design rules, guide parasitic extraction

Qualifications

• 8+ years of experience in full-custom analog and mixed-signal layout for production silicon.
• 8+ years of hands-on experience with Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification.
• Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out.
• Experience defining and implementing layout methodologies for matching, shielding, and noise isolation in mixed-signal environments.
• Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints and implementation decisions.
• Experience managing and mentoring layout engineers and coordinating work with external contractors.

Responsibilities

• Lead full-custom layout of complex analog and mixed-signal blocks including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon targeting VR and AR wearable platforms.
• Define and enforce analog layout methodologies, design rules, and best practices across the physical design team.
• Drive parasitic‑aware layout strategies to meet stringent noise, matching, and signal integrity requirements for mixed‑signal designs.
• Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results.
• Own physical verification closure including DRC, LVS, and antenna checks across advanced process nodes.
• Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts.
• Provide technical guidance and layout direction to other engineers on the team, reviewing layouts and driving consistency in methodology.
• Partner with process technology and design kit teams to evaluate new process nodes and contribute to PDK qualification for analog layout.
• Identify and resolve layout‑induced performance issues through post‑layout simulation analysis and iterative design refinement.
• Own long‑term physical design roadmaps and methodology investments that scale across multiple silicon programs.
• Manage layout contractors to deliver high‑quality final GDS on schedule and in alignment with design specifications.

Tools

Cadence Virtuoso

Job description

Summary

Meta's Silicon Engineering organization is building custom silicon solutions that power the next generation of virtual and augmented reality products, including wearable devices and spatial computing platforms. We are seeking an experienced Analog Layout Lead to drive the physical implementation of complex analog and mixed-signal circuits for custom chips at the heart of Meta's reality labs hardware portfolio. In this role, you will own the full-custom layout of high-performance analog blocks, define physical design methodologies, and partner closely with circuit design and verification teams to deliver silicon that meets aggressive power, performance, and area targets.

Required Skills

Analog Layout Lead, Silicon Engineering Responsibilities:

1. Lead full-custom layout of complex analog and mixed-signal blocks including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon targeting VR and AR wearable platforms

2. Define and enforce analog layout methodologies, design rules, and best practices across the physical design team

3. Drive parasitic‑aware layout strategies to meet stringent noise, matching, and signal integrity requirements for mixed‑signal designs

4. Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus‑schematic and parasitic extraction results

5. Own physical verification closure including DRC, LVS, and antenna checks across advanced process nodes

6. Establish floorplanning and integration strategies for analog IP blocks within larger mixed‑signal SoC contexts

7. Provide technical guidance and layout direction to other engineers on the team, reviewing layouts and driving consistency in methodology

8. Partner with process technology and design kit teams to evaluate new process nodes and contribute to PDK qualification for analog layout

9. Identify and resolve layout‑induced performance issues through post‑layout simulation analysis and iterative design refinement

10. Own long‑term physical design roadmaps and methodology investments that scale across multiple silicon programs

11. Manage layout contractors to deliver high‑quality final GDS on schedule and in alignment with design specifications

Minimum Qualifications

1. 8+ years of experience in full‑custom analog and mixed‑signal layout for production silicon in advanced CMOS process nodes (28nm or below)

2. 8+ years of hands‑on experience with industry‑standard layout tools such as Cadence Virtuoso for schematic‑driven layout, parasitic extraction, and physical verification

3. Experience leading layout of high‑performance analog blocks such as PLLs, voltage regulators, data converters, or high‑speed interfaces from concept through tape‑out

4. Experience defining and implementing layout methodologies for matching, shielding, and noise isolation in mixed‑signal environments

5. Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints and implementation decisions

6. Experience managing and mentoring layout engineers and coordinating work with external contractors

Preferred Qualifications

1. Familiarity with post‑layout simulation flows including RC extraction and back‑annotated verification using tools such as Spectre or Calibre

2. Experience contributing to or evaluating process design kits and design rule documentation for new process node bring‑up

3. Experience with analog layout for consumer wearable, mobile, or IoT SoCs where power, area, and reliability constraints are critical

4. Experience with 3D stacking technologies and advanced packaging layout considerations

5. Track record of developing reusable analog layout templates or parameterized cells that improve team‑wide layout efficiency and consistency

Public Compensation

$178,000/year to $250,000/year + bonus + equity + benefits

Industry

Internet

Equal Opportunity

Meta is proud to be an Equal Employment Opportunity and Aff… We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E‑Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].