Staff Analog IC Layout Engineer (Block & Chip)

Elevate; San Diego (CA); On-site; USD 145,000 - 175,000; Full time

Job summary

Elevate in San Diego seeks a Staff Analog Layout Engineer to own the physical layout and verification of advanced analog and mixed-signal ICs for the ATE market. You will work across block-level and full-chip layouts using 65nm to 100+V BCD processes.

You will collaborate with analog design teams to optimize area, performance, and reliability, perform LVS/DRC checks, and drive tapeouts while mentoring engineers on best practices and layout flows.

Qualifications

• Bachelor’s degree in Electrical Engineering or a related field.
• 8+ years of analog/mixed-signal IC layout experience.
• Strong understanding of analog CMOS circuits and device physics.
• Experience with LVS/DRC verification and manufacturability.

Responsibilities

• Perform physical layout of analog and mixed-signal ICs at block and full-chip levels.
• Develop floorplans and optimize placement for area, performance, and power.
• Verify LVS and DRC to ensure layout accuracy and process-rule compliance.
• Collaborate with design engineers to translate circuit requirements into layouts.
• Partner with cross-functional teams to optimize chip performance and tapeouts.
• Troubleshoot layout, verification, and manufacturability issues.

Skills

Analog layout

IC design knowledge

LVS/DRC verification

EDA tools

Device physics

Layout optimization

Scripting SKILL

Education

Bachelors in Electrical Engineering

Tools

Cadence

Mentor Graphics

Tanner

Calibre

Job description

As a Staff Analog Layout Engineer, you will take technical ownership of the physical layout and verification of complex analog and mixed-signal integrated circuits for the ATE market. You will work across both block-level and full-chip layout using advanced process technologies ranging from 65nm CMOS to 100+V BCD.

This role offers the opportunity to solve complex layout challenges, collaborate closely with analog design engineers, and influence layout strategy across projects. You will apply your expertise in matching, parasitics, reliability, and manufacturability while helping establish best practices and drive designs through successful tapeout.

Responsibilities

• Perform physical layout of analog and mixed-signal integrated circuits at both the block and full-chip level
• Develop floorplans and optimize component placement for area, performance, and power
• Perform LVS and DRC verification to ensure layout accuracy and compliance with process design rules
• Collaborate closely with design engineers to translate circuit requirements into high-quality physical layouts
• Partner with digital design, packaging, and other cross-functional teams to optimize overall chip performance
• Troubleshoot and resolve layout, verification, and manufacturability issues

• Bachelor’s degree in Electrical Engineering or a related field
• Minimum of 8 years of professional experience in analog and mixed-signal IC layout design
• Strong understanding of analog CMOS circuits and device physics
• Solid knowledge of the IC design, qualification, and manufacturing lifecycle
• Hands-on experience with industry-standard EDA tools such as Cadence, Mentor Graphics, or Tanner
• Proficiency in LVS and DRC verification using Cadence or Mentor tools

Preferences

• Experience with high-voltage (100V+) BCD, LDMOS, and STI layout
• Experience with mixed-voltage designs involving multiple supply rails and power domains
• Experience with high-speed, multi-Gbps circuit layout
• Experience with high-accuracy and precision analog circuit layout
• Experience with high-resolution data converter layout
• Experience with BiCMOS process technologies
• Programming and scripting experience, particularly with SKILL and Calibre scripts

The anticipated annual base salary range for this position is$145,000.00 to $175,000.00. Actual compensation will be determined based on factors such as experience, skills, qualifications, education, location, and business needs.

In addition to base salary, employees may be eligible for incentive compensation and a comprehensive benefits package. This salary range represents the Company's good-faith estimate of the compensation it reasonably expects to pay for this position at the time of posting.