Senior Analog Design Lead - HBM IP

Micron Technology, Inc.; Richardson (TX); Vor Ort; USD 140.000 - 200.000; Vollzeit

Zusammenfassung

Micron Technology, Inc. seeks a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products.

This role drives end-to-end success of HBM solutions, focusing on performance, power efficiency, and reliability. You will supervise high-speed transmitters/receivers, clock generation, biasing and calibration circuits, power regulation, and IP interfaces across subsystems, collaborating with layout,

Qualifikationen

• MS or PhD in Electrical Engineering or related field.
• 10–15+ years of analog/mixed-signal IC design experience.
• Proven expertise in high-speed interface design, PLL/DLL/CDR clocks, and power management circuits.
• Experience with analog IP integration at subsystem or SoC level.
• Proficiency in SPICE simulations and silicon bring-up.

Aufgaben

• Lead the design and own critical HBM analog circuits (transmitters/receivers, clocks).
• Define and manage IP interfaces, power domains, clocking, and reset schemes across subsystems.
• Perform pre-layout and post-layout simulations; drive layout-aware optimizations.
• Collaborate across analog, digital, system, packaging, and test teams.

Kenntnisse

High-speed interface

Clocking circuits

Power management

Analog IP integration

SPICE simulation

Silicon bring-up

Layout floorplanning

Noise & jitter

Analytical skills

Ausbildung

MS or PhD in Electrical Engineering

Tools

None

Jobbeschreibung

Micron Technology, Inc. seeks a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products.

This role drives end-to-end success of HBM solutions, focusing on performance, power efficiency, and reliability. You will supervise high-speed transmitters/receivers, clock generation, biasing and calibration circuits, power regulation, and IP interfaces across subsystems, collaborating with layout,