Senior SerDes Architect – TX/RX Datapath Lead

d-Matrix; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

d-Matrix is seeking a senior SerDes design engineer in Santa Clara to own transistor-level SerDes blocks through silicon bring-up. You will drive the transmit and receive datapaths, develop high-speed interface architectures, and work closely with layout, SI, and firmware teams to deliver working silicon on next-generation IO chiplets.

You will model, simulate, and verify complex equalization and signaling paths, conduct budgets, and contribute to testboard design while supporting backend

Qualifications

• Ownership of SerDes transmitter/receiver datapath through to working silicon in a high-speed link.
• Experience in transistor-level design for SerDes, including output drivers and CTLE/DFE/FFE architectures.
• Strong jitter/noise budgeting, modeling, and verification methodology.
• Proficiency with advanced CMOS processes (FinFET/GAA) and analog/mixed-signal CAD tools.
• Experience bring-up, bench debugging with high-speed lab equipment.

Responsibilities

• Own transistor-level design of SerDes transmit path: SST and/or CML drivers, pre-driver, serializer, and transmit FFE.
• Own transistor-level design of the receive front-end: termination, ESD input network, CTLE, VGA, samplers, ADC front-ends.
• Design and verify equalization path (DFE/FFE) and conduct architecture trade studies.
• Derive block-level specs from link budgets and defend in design reviews.
• Build verification environment: testbenches, PVT coverage, Monte Carlo, post-layout simulations.

Skills

SerDes design

Transmitter datapath ownership

Receiver datapath ownership

Jitter analysis

Analog/mixed-signal design

Education

BS/MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

MATLAB

Python

Post-layout simulation

Job description

d-Matrix is seeking a senior SerDes design engineer in Santa Clara to own transistor-level SerDes blocks through silicon bring-up. You will drive the transmit and receive datapaths, develop high-speed interface architectures, and work closely with layout, SI, and firmware teams to deliver working silicon on next-generation IO chiplets.

You will model, simulate, and verify complex equalization and signaling paths, conduct budgets, and contribute to testboard design while supporting backend