Senior Analog Design Architect - DDR/PLL Expert

Renesas; Duluth (GA); On-site; USD 120,000 - 180,000; Full time

Job summary

Renesas is seeking an experienced Architect to design and verify CMOS analog blocks for custom ASICs, including Tx, Rx and PLL, with a focus on high performance, low power and tight timelines.

You will lead DDR I/O interface design, collaborate with digital, verification and test teams, mentor junior engineers, and produce detailed design documentation while ensuring signal integrity, reliability and manufacturability.

Qualifications

• Advanced degree in Electronics/Microelectronics Engineering or related discipline.
• 10–15 years of analog circuit design experience.
• Expertise in high-speed DDR I/O interface design and optimization - emphasis on DDR5/DDR6 IO architecture.
• In-depth knowledge of analog Rx/Tx design, including signal integrity and noise immunity.
• Proficiency with analog design tools (e.g., Cadence Virtuoso, Maestro, Spectre, HSPICE) and simulation techniques.

Responsibilities

• Architect and verify CMOS analog blocks (Tx, Rx, PLL) for custom ASICs.
• Develop high-speed DDR I/O interfaces with emphasis on signal integrity.
• Collaborate with digital design, verification, and test teams.
• Analyze Si ATE/bench data using Excel/MATLAB/scripts to extract actionable insights.
• Provide technical leadership and mentorship to junior engineers.
• Conduct comprehensive simulations and testing to validate performance and reliability.
• Create detailed design documentation and reports.
• Stay abreast of industry trends and pursue low-power design innovations.
• Ensure layouts meet high analog standards for matching and performance.

Skills

DDR I/O design

Signal integrity

Analog design principles

Documentation

Education

Advanced degree in Electronics/Microelectronics Engineering

Tools

Cadence Virtuoso

Maestro

Spectre

HSPICE

Job description

Renesas is seeking an experienced Architect to design and verify CMOS analog blocks for custom ASICs, including Tx, Rx and PLL, with a focus on high performance, low power and tight timelines.

You will lead DDR I/O interface design, collaborate with digital, verification and test teams, mentor junior engineers, and produce detailed design documentation while ensuring signal integrity, reliability and manufacturability.