Senior Digital Design Architect — Low-Power

Renesas; Chandler (AZ); On-site; USD 120,000 - 180,000; Full time

Job summary

Renesas Electronics seeks a Senior Digital Design Engineer to craft power- and area-optimized digital circuits for complex mixed-signal applications in Chandler, AZ. You will transform high-level requirements into RTL, integrate at the top level, and collaborate with Analog and Verification teams to deliver silicon solutions.

The role requires 5+ years in digital design, solid knowledge of ASIC methodologies, and proficiency with Verilog/SystemVerilog and verification tools.

Qualifications

• 5+ years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management.
• Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
• Strong understanding of ASIC design methodology.
• Strong understanding of Lint, CDC & RDC tools.
• Strong understanding of block-level & chip-level verification techniques.
• Strong & proven ability to debug both RTL & gate-level simulations.
• Mandatory competence in written and verbal English.
• Willingness to travel domestically or internationally on short notice.
• Ability to work independently and collaboratively.
• Preferred: experience with mixed-signal design methodologies.
• Preferred: experience developing design constraints and hand-off to P&R.
• Preferred: experience with STA and timing closure.
• Preferred: experience with low-power design techniques, including clock and power gating (UPF).
• Preferred: experience with power analysis and optimization.
• Preferred: experience with advanced verification methodologies (UVM).
• Preferred: experience with industry-standard protocols such as AMBA or I2C.

Responsibilities

• Interpret high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
• Support full product lifecycle from concept to mass-production; communicating closely with wider organization through the various stages of silicon development.
• Work closely with Analog and Verification engineers to deliver high-quality silicon solutions.
• Ensuring digital development process is state-of-art and achieves budget, schedule, and project deliverable goals.
• Designing digital RTL that meets timing, area, power and any adhering standards specifications.
• Integrating design at the top level and running block & top-level simulations.
• Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF.
• Working closely with P&R team to generate a layout that meets timing, area, and power requirements.
• Support DFT strategy and implementation,and review test case development.
• Assisting with top level test-bench debug,and running RTL & gate level simulations
• Working with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification.
• Supporting analog team to develop AMS, SystemVerilog or Verilog-real behavioral models.
• Developing detailed block & chip level design documents and collateral.
• Holding and participating in key design reviews and completion of various checklists.
• Perform silicon evaluation as required.
• Document device errata, develop work-around solutions, implement engineering changes when necessary.

Skills

Digital design

ASIC design methodology

RTL/Verilog/SystemVerilog

Debug RTL & gate-level

Lint/CDC/RDC tools

UVM

Mixed-signal design

STA/timing closure

UPF low-power design

Power analysis & optimization

Verilog/SystemVerilog verification

AMBA/I2C protocols

English communication

Education

Electrical Engineering / Electronics / Computer Engineering / Computer Science degree

Tools

Verilog

SystemVerilog

UVM

Verif Tools (Lint/CDC/RDC)

Job description

Renesas Electronics seeks a Senior Digital Design Engineer to craft power- and area-optimized digital circuits for complex mixed-signal applications in Chandler, AZ. You will transform high-level requirements into RTL, integrate at the top level, and collaborate with Analog and Verification teams to deliver silicon solutions.

The role requires 5+ years in digital design, solid knowledge of ASIC methodologies, and proficiency with Verilog/SystemVerilog and verification tools.