Senior SoC Digital Architect & RTL Lead

SmartRecruiters, Inc.; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Renesas is seeking an experienced Sr Staff Digital Design Engineer to join the Analog & Connectivity Business Group. You will architect, design, integrate, and implement advanced digital and mixed-signal ICs and SoCs, collaborating across architecture, verification, DFT, and physical design teams.

The ideal candidate has strong RTL, SoC integration, and design signoff expertise, with a track record delivering silicon products in complex SoC environments.

Qualifications

• MSEE or Ph.D. in Electrical Engineering with 8+ years of industry experience, or BSEE with 12+ years.
• Strong background in digital IC and SoC architecture, design, and implementation.
• Proven experience with SoC interconnects and protocols including AHB, APB, AXI, USB, I2C/I3C, SPI, and UART.
• Hand-on RTL design using Verilog/SystemVerilog and complete ASIC/SoC development flow.

Responsibilities

• Define digital architecture and micro-architecture for complex mixed-signal and SoC products.
• Develop high-quality RTL using Verilog/SystemVerilog and participate in design reviews.
• Drive SoC and subsystem integration, including internal bus architectures and peripheral interfaces.
• Develop and validate timing constraints, synthesis scripts, and implementation flows.
• Analyze CDC, RDC, Lint, and timing issues to achieve design signoff.
• Collaborate with verification teams on test planning, coverage closure, and debugging.
• Support DFT implementation including scan, MBIST, JTAG, and production test methodologies.
• Work with physical design teams to achieve power, performance, and area goals.
• Perform silicon bring-up, debug, characterization, and root-cause analysis of silicon issues.
• Create and maintain design documentation throughout the development cycle.
• Contribute to technology and architecture definition for future product generations.

Skills

Digital IC design

RTL design

SoC integration

Verilog/SystemVerilog

STA

DFT

Multi-clock design

Memory architectures

Education

MSEE or Ph.D. EE

BSEE with 12+ years

Tools

Synopsys Design Compiler

PrimeTime

SpyGlass

VC Formal

Verdi

Cadence design tools

Job description

Renesas is seeking an experienced Sr Staff Digital Design Engineer to join the Analog & Connectivity Business Group. You will architect, design, integrate, and implement advanced digital and mixed-signal ICs and SoCs, collaborating across architecture, verification, DFT, and physical design teams.

The ideal candidate has strong RTL, SoC integration, and design signoff expertise, with a track record delivering silicon products in complex SoC environments.