Senior AIML-Driven Design & Verification Architect

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 174,000 - 353,000; Full time

Job summary

Hewlett Packard Enterprise seeks a Senior AIML enhanced Design/Verification Methodology Engineer to advance verification strategies for complex digital designs using AIML methods.

You will architect and maintain AIML-enabled design verification environments, collaborate with design and system teams to ensure silicon quality from RTL to tapeout, and push innovative AI-driven verification across the flow.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or Computer Science (or equivalent).
• 3–5 years of hands-on AIML methods experience including agents, skills, APIs, models for design/verification.
• 5–7 years in RTL design and verification infrastructure; strong SystemVerilog experience.

Responsibilities

• Architect, build, and maintain AIML-enhanced or agentic design/verification environments.
• Develop, verify, and optimize UVM-based testbenches and verification plans with AI support.
• Automate RTL generation from specs and drive resolution of design issues with cross-functional teams.
• Evaluate industry tools and approaches for verification and emulation.

Skills

AIML methods

SystemVerilog

Digital design fundamentals

Cross-functional collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master's or PhD in Electrical Engineering or Computer Science

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

JasperGold

Palladium/Protium/Veloce

Job description

Hewlett Packard Enterprise seeks a Senior AIML enhanced Design/Verification Methodology Engineer to advance verification strategies for complex digital designs using AIML methods.

You will architect and maintain AIML-enabled design verification environments, collaborate with design and system teams to ensure silicon quality from RTL to tapeout, and push innovative AI-driven verification across the flow.