Senior Methodologist for AIML Enhanced Design/Verification

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 174,000 - 353,000; Full time

Job summary

Hewlett Packard Enterprise seeks a Senior AIML enhanced Design/Verification Methodology Engineer to advance verification strategies for complex digital designs using AIML methods.

You will architect and maintain AIML-enabled design verification environments, collaborate with design and system teams to ensure silicon quality from RTL to tapeout, and push innovative AI-driven verification across the flow.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or Computer Science (or equivalent).
• 3–5 years of hands-on AIML methods experience including agents, skills, APIs, models for design/verification.
• 5–7 years in RTL design and verification infrastructure; strong SystemVerilog experience.

Responsibilities

• Architect, build, and maintain AIML-enhanced or agentic design/verification environments.
• Develop, verify, and optimize UVM-based testbenches and verification plans with AI support.
• Automate RTL generation from specs and drive resolution of design issues with cross-functional teams.
• Evaluate industry tools and approaches for verification and emulation.

Skills

AIML methods

SystemVerilog

Digital design fundamentals

Cross-functional collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master's or PhD in Electrical Engineering or Computer Science

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

JasperGold

Palladium/Protium/Veloce

Job description

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description

We are seeking a Senior AIML enhanced Design/Verification Methodology Engineer to join our team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs using AIML enhanced methodologies. You will architect, build, and maintain AIML enhanced or agentic solutions for design and verification environments with applications to all phases of design and verification closure. You will collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout. This is a high-impact position for someone who thrives on solving intricate design/verification challenges using AIML methodologies.

Key Responsibilities

• Use both “classical” and Generative-AI methodologies to architect, develop, and maintain agents, skills, and other AI based design and verification infra-structures. The ideal person will have balanced knowledge of chip design and AIML methodologies to contribute meaningfully to the creation of architecture, design, verification, and physical design assets. These includes but not limited to:
• Creating UVM-based testbench environments from ground up or enhance the existing ones using AI. Creating verification plans with clear coverage goals and closure criteria. Performing root cause analysis of failures and work with design teams to drive resolution.
• Automating generation of RTL from spec.
• Evaluation of industry tools.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent).
• 3 -5 years of direct hands-on experience with AIML methods, concepts and workflows — including experience in creating agents, skills, APIs, model, etc. for Design/Verification problem.
• 5 - 7 years of experience in production development of RTL design and verification infrastructure. Strong experience in SystemVerilog for design or verification.
• Solid understanding of digital design fundamentals (RTL, timing, synthesis constraints).
• Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Effective communication and collaboration skills in cross-functional team settings.

Preferred Qualifications

• Master's or Ph.D. in Electrical Engineering or Computer Science.
• Experience with formal verification tools and techniques (e.g., JasperGold, VC Formal) is a plus. Experience with emulation and FPGA prototyping platforms (e.g., Palladium, Protium, Veloce) is also a plus.
• Industry conference/peer reviewed journal publications in the design/verification methodology development and/or AIML.

Why Join Us?

You’ll work on challenging, cutting-edge designs alongside a talented engineering team that values innovation, quality, and continuous learning. We offer competitive compensation, comprehensive benefits, and opportunities for professional growth.

Accessibility

HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form here. Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Job

Engineering

Job Level

TCP_05

The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.

– United States of America: Annual Salary USD 174,000 - 352,500 in California

The listed salary range reflects base salary. Variable incentives may also be offered.

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.