Senior AIML Design & Verification Methodologist

HITEC; Sunnyvale, Northern (CA, KY); Hybrid; USD 174,000 - 353,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Senior AIML Enhanced Design/Verification Methodology Engineer to develop and execute comprehensive verification strategies for complex digital designs using AIML methodologies. You will architect, build, and maintain AIML-enhanced solutions for design and verification environments from RTL to tapeout.

The role collaborates closely with design and systems teams to ensure silicon quality and entails high-impact challenges in AIML-enabled verification

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent).
• 3-5 years of hands-on AIML methods, concepts and workflows— including agents, skills, APIs, model creation for Design/Verification.
• 5-7 years in production development of RTL design and verification infrastructure; strong SystemVerilog experience.
• Solid understanding of RTL, timing, and synthesis constraints.
• Experience with Synopsys VCS, Cadence Xcelium, Mentor Questa.

Responsibilities

• Architect, develop, and maintain AI-based design and verification infra-structures using AIML methods; contribute to architecture, design, verification, and physical design assets.
• Create UVM-based testbenches from ground up or enhance existing ones; develop verification plans with coverage goals and closure criteria; perform root cause analysis of failures.
• Automate generation of RTL from specifications; evaluate industry tools.

Skills

AIML methods

SystemVerilog

RTL design

Verification infra

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Palladium

Protium

Veloce

Job description

Hewlett Packard Enterprise is seeking a Senior AIML Enhanced Design/Verification Methodology Engineer to develop and execute comprehensive verification strategies for complex digital designs using AIML methodologies. You will architect, build, and maintain AIML-enhanced solutions for design and verification environments from RTL to tapeout.

The role collaborates closely with design and systems teams to ensure silicon quality and entails high-impact challenges in AIML-enabled verification