AI SoC Cache Designer: RTL & GPU Cache Innovation

Intel Corporation; Santa Clara (CA); On-site; USD 221,000 - 312,000; Full time

Job summary

Intel is seeking a SoC Cache Design Engineer to drive cache subsystem design for AI SoCs. You will lead microarchitecture, RTL coding, and verification to deliver high‑quality, power‑aware cache designs for Intel's AI hardware solutions.

Responsibilities include defining microarchitecture, RTL implementation, and collaboration with verification and physical design teams. Requires extensive RTL experience and expertise in AXI/AHB protocols, with on-site work in Santa Clara, CA.

Qualifications

• 12+ years of RTL design experience for ASIC/SoC development.
• Advanced proficiency in Verilog and SystemVerilog.
• Experience with AXI/AHB bus protocols and embedded processor architectures.
• Ability to address clock domain crossings, power optimization, and timing closure.
• Scripting in Python or TCL for automation and design flow customization.

Responsibilities

• Evaluate architectural trade-offs to align design features with performance targets, power constraints, and system limitations.
• Define and document microarchitecture specifications for complex SoC IP blocks, implement RTL in Verilog/SystemVerilog, and deliver synthesis- and timing-clean designs.
• Collaborate with verification teams to ensure comprehensive validation and coverage of all design aspects.
• Develop and maintain timing constraints for IP blocks, supporting physical design teams in synthesis, timing closure, and formal equivalence checks.
• Lead silicon bring-up efforts, including post-silicon validation, debug, and performance analysis.
• Mentor junior engineers and contribute to advancing best practices for design methodology and quality assurance.

Skills

RTL design

Verilog/SystemVerilog

AXI/AHB

Embedded processor architectures

Python

TCL

SoC integration

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in relevant field

PhD in relevant field

Tools

VCS

Questa

IES

Spyglass

Vivado

Quartus II

Job description

Intel is seeking a SoC Cache Design Engineer to drive cache subsystem design for AI SoCs. You will lead microarchitecture, RTL coding, and verification to deliver high‑quality, power‑aware cache designs for Intel's AI hardware solutions.

Responsibilities include defining microarchitecture, RTL implementation, and collaboration with verification and physical design teams. Requires extensive RTL experience and expertise in AXI/AHB protocols, with on-site work in Santa Clara, CA.