Senior Engineer, Physical Design AI/ML

Samsungsemiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks PTO

Diversity & Benefits

Flexible work policy

Job summary

Samsung Semiconductor Inc in San Jose seeks a Senior Physical Design AI/ML Engineer for the Logic Pathfinding Lab. You will apply AI/ML to improve design simulation accuracy and throughput, and contribute to DTCO knob optimization for sub-2nm nodes.

The role requires a PhD with hands-on RTL synthesis, place & route, PDK generation, and collaboration across teams. Strong Python/C++ and ML frameworks are essential, with onsite presence in San Jose.

Qualifications

• PhD with industry experience preferred.
• RTL synthesis, place and route, and timing analysis skills.
• Understanding of clock and power delivery network schemes.
• Hands-on experience on ML/DL projects for scientific/engineering applications (regression, surrogate modeling, inverse design, GNNs).

Responsibilities

• Design, build, and implement ML/gen models to optimize chip layouts for PPA efficiency.
• Automate Floorplanning, Placement and Routing, Clock Tree Synthesis.
• Automate DRC and LVS checks with exploratory PDKs.
• Collaborate to automate exploratory PDK generation and QA systems.
• Apply ML to extract correlations among data across domains (device, RO benchmarks, blocks).
• Develop benchmarking capability from available data and share assessments with R&D.

Skills

Python

C++

Machine Learning

PyTorch

TensorFlow

Bayesian optimization

Active learning

RTL synthesis

Place and route

Timing analysis

Communication

Education

PhD

Tools

EDA tools

Synthesis tools

Layout tools

Job description

Job Title Senior Physical Design AI/ML Engineer, Logic Pathfinding Lab

We are looking for physical design engineers who have demonstrated skills in applying AI / Machine Learning tools in improving design simulation accuracy and throughput in predicting design performance, power, and area (PPA). Experience in optimization of design-technology co-optimization (DTCO) knobs in advanced logic nodes (2nm or beyond) is preferred.

What You’ll Do

The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose. He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea. The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-2nm technology nodes. The candidate should have demonstrated skills and experience in standard cell architecture creation, logic cell library characterizations Place and Route, Process Design Kit (PDK) generation, and a strong understanding of Logic process integration. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia.

• Design, build, and implement machine learning and generative models to optimize chip layout designs to maximize performance, power, and area (PPA) efficiency, while using explicit domain knowledge of hardware design rules and constraints


• Automate and accelerate Design Implementation steps such as Floor-planning, Placement and Routing, Clock Tree Synthesis, using exploratory PDKs developed by the team


• Automate and accelerate Verification steps such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) Checks using exploratory PDKs developed by the team


• Collaborate with other team members to automate all aspects of exploratory PDK generation, including developing automated QA systems


• Applying machine learning techniques to extract and develop correlations among data in different domains, e.g. device, RO benchmark circuits, larger circuit blocks, at different operating conditions


• Develop internal benchmarking capability based on available data, modeling, or learning from multiple sources, and create assessments to share with internal R&D team


• Complete other responsibilities as assigned.

Location

Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy

Reports to

Sr Director

Direct Reports

N/A

What You Bring

• PhD with industry experience preferred


• RTL synthesis, place and route, and timing analysis skills


• Understanding of clock and power delivery network schemes


• Hands-on experience on machine learning or deep learning projects for scientific and/or engineering applications, e.g., regression, surrogate modeling, inverse design, graph neural networks


• Strong Python and/or C++ skills, including expertise in machine learning packages like PyTorch and Tensorflow


• Experience in using Bayesian optimization and/or active learning frameworks for design space exploration


• Expertise with agentic AI frameworks (LangGraph, CrewAI, ADK)


• You’re inclusive, adapting your style to the situation and diverse global norms of our people.


• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.


• You're collaborative, building relationships, humbly offering support and openly welcoming approaches.


• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

Preferred qualifications

• Familiarity with state-of-the-art AI workloads and their compute and memory requirements


• Experience with setting up and optimization of a local, private, compute cluster to run latest LLM models


• Proficiency in EDA tools for synthesis and layout


• Prior experience using generative AI for chip design/optimization

Status

#LI-SF1

What We Offer

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance.

This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

Benefits

Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.

Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.

Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.

Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.

Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.

Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.

Base Pay Range

$138,000 — $206,000 USD

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

Our Commitment to Innovation and Fairness

At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.

Recruiting Agency Policy

We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.

Applicant AI Use Policy

At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.

Trade Secret Notice

By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

Applicant Privacy Policy

https://semiconductor.samsung.com/about-us/careers/us/privacy/