Senior Verification Engineer, HBM for AI/ML Systems

Socket.dev; Richardson (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Micron Technology in Richardson, TX, seeks a Senior Verification Engineer to drive IP- and SoC-level verification for next-generation HBM products. You will work with Design, Product Engineering, and Business Units to shape the verification roadmap and ensure robust pre-/post-silicon validation.

The role requires strong testbench architecture knowledge, experience with Verilog digital verification, and evidence of working across custom and RTL design verification flows.

Qualifications

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of relevant verification engineering experience, including 3+ years in digital (Verilog), analog (FastSpice), or mixed-signal verification.
• 2+ years in custom design verification or RTL design verification flows.
• Strong problem-solving and communication skills.

Responsibilities

• Develop and implement verification plans and architecture for IP-level and SoC-level verification of HBM designs.
• Support co-verification of the system and engage with customers to gather feedback.
• Build and improve verification methodology components and GenAI applications for HBM verification cycles.
• Evaluate and debug pre-silicon and post-silicon issues and explore new verification architectures.

Skills

Verilog digital verification

Analog/mixed-signal verification

Communication skills

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree in Electrical/Computer Engineering (preferred)

Tools

Verification tooling

GenAI in verification

Job description

Micron Technology in Richardson, TX, seeks a Senior Verification Engineer to drive IP- and SoC-level verification for next-generation HBM products. You will work with Design, Product Engineering, and Business Units to shape the verification roadmap and ensure robust pre-/post-silicon validation.

The role requires strong testbench architecture knowledge, experience with Verilog digital verification, and evidence of working across custom and RTL design verification flows.