Senior AI-Driven IC Layout Engineer (PCells & Optimization)

Anite; Calabasas (CA); On-site; USD 129,000 - 216,000; Full time

Benefits offered by this job

Medical, dental and vision

Health Savings Account

401(k) Plan

Flexible Time Off

Job summary

Keysight is seeking an R&D Engineer to advance RFIC layout automation for RFIC, analog and microwave design applications. You will work on parameterized cell development, lattice generation, and machine learning-enabled optimization to accelerate semiconductor productivity.

The role requires strong RFIC/analog experience, proficiency in Python/C++, and collaboration with RFIC designers and software engineers to deliver scalable EDA capabilities in a production environment.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, or related discipline.
• Strong hands-on experience in RFIC, analog, microwave, or mixed-signal design.
• Deep expertise in layout automation, parameterized layout generation, and PCell development.
• Strong understanding of semiconductor layout methodologies, design rules, physical verification, and EM-aware design practices.
• Experience developing software using Python and/or C++.
• Strong understanding of computational geometry, algorithms, and software architecture.
• Experience with circuit simulation, optimization workflows, and semiconductor design automation tools.
• Proven problem-solving and analytical skills with the ability to translate complex engineering workflows into scalable automation solutions.

Responsibilities

• Develop advanced PCells, Python-based cells, and automated layout generation capabilities for RFIC, microwave, and analog components.
• Design and implement layout automation solutions including geometry generation, placement, routing, symmetry enforcement, design-rule-aware synthesis, and EM-aware design flows.
• Integrate layout automation with circuit and EM simulation environments to enable automated design optimization, parameter exploration, and design-space analysis.
• Develop intelligent optimization frameworks leveraging machine learning, surrogate modeling, Bayesian optimization, and reinforcement learning techniques to accelerate design convergence.
• Build scalable software solutions in Python and C++ that support next-generation AI-assisted semiconductor design workflows.
• Collaborate with RFIC designers, modeling experts, and software engineers to deliver production-quality EDA capabilities that improve design productivity and product performance.

Skills

RFIC design

Analog/microwave

PCell development

Python

C++

EM-aware design

Design rules

Machine learning for design

Education

MS or PhD in Electrical/Computer Engineering or related

Tools

Cadence Virtuoso

Job description

Keysight is seeking an R&D Engineer to advance RFIC layout automation for RFIC, analog and microwave design applications. You will work on parameterized cell development, lattice generation, and machine learning-enabled optimization to accelerate semiconductor productivity.

The role requires strong RFIC/analog experience, proficiency in Python/C++, and collaboration with RFIC designers and software engineers to deliver scalable EDA capabilities in a production environment.