AI-Driven EDA Layout Intern for RFIC & Analog

Keysight Technologies SAles Spain SL.; Calabasas, Northern (CA, KY); Hybrid; USD 55,000 - 74,000; Full time

Job summary

Keysight is seeking an EDA AI/ML Layout Engineering Intern to contribute to AI-powered layout automation for RFIC and analog IC design. You will work with EDA engineers and AI researchers on automated layout generation, PCell development, and design space exploration.

Ideal candidates are pursuing a Master’s or PhD in a related field with strong Python skills and exposure to ML frameworks. Relocation is available; CPT/work authorization requirements apply.

Qualifications

• Pursuing a Master's or PhD in a related technical field.
• Strong Python programming.
• Familiarity with ML frameworks such as PyTorch, TensorFlow, or scikit-learn.
• Solid understanding of data structures, algorithms, and OOP.
• Strong analytical and problem-solving skills.
• Interest in AI/ML applied to engineering design automation.

Responsibilities

• Develop AI and ML solutions for RFIC and analog layout automation
• Research and prototype ML techniques for layout synthesis and design optimization
• Assist in the development of PCells and layout generation workflows
• Work on geometric, topological, and rule-aware layout generation techniques
• Contribute to surrogate modeling and design space exploration frameworks
• Build data generation, training, and evaluation pipelines for AI-driven EDA workflows
• Develop software components in Python and potentially C++ under mentorship
• Evaluate AI-assisted design methodologies using real-world semiconductor design problems
• Collaborate with EDA engineers and RFIC designers to validate solutions

Skills

Python

Algorithms

Problem solving

Analytical thinking

AI/ML interest

Education

Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or related field

Tools

PyTorch

TensorFlow

scikit-learn

Job description

Keysight is seeking an EDA AI/ML Layout Engineering Intern to contribute to AI-powered layout automation for RFIC and analog IC design. You will work with EDA engineers and AI researchers on automated layout generation, PCell development, and design space exploration.

Ideal candidates are pursuing a Master’s or PhD in a related field with strong Python skills and exposure to ML frameworks. Relocation is available; CPT/work authorization requirements apply.