AI/ML EDA Layout Engineer Intern

InternHunt; Calabasas, Northern (CA, KY); Hybrid; USD 84,000 - 90,000; Full time

Benefits offered by this job

Relocation assistance

Job summary

Keysight EDA is seeking an AI/ML Layout Engineering Intern to help automate RFIC and analog layout generation. You will work with EDA engineers, AI researchers, and RFIC domain experts to build intelligent workflows that boost designer productivity and accelerate chip development.

The role emphasizes Python and possibly C++ development, with exposure to ML frameworks and design automation concepts in a collaborative, Agile setting. Relocation is available for California candidates.

Qualifications

• Pursuing Master's or PhD in a technical field.
• Strong Python programming ability.
• Familiarity with PyTorch, TensorFlow, or scikit-learn.
• Solid understanding of data structures, algorithms, and OO programming.
• Strong analytical and problem-solving skills.
• Interest in AI/ML for engineering design automation.

Responsibilities

• Develop AI/ML solutions for RFIC and analog layout automation.
• Research & prototype ML techniques for layout synthesis and design optimization.
• Assist in the development of PCells and layout generation workflows.
• Work on geometric, topological, and rule-aware layout generation techniques.
• Contribute to surrogate modeling and design-space exploration frameworks.
• Build data generation, training, and evaluation pipelines for AI-driven EDA workflows.
• Develop software components in Python and possibly C++ under mentorship.
• Collaborate with EDA engineers and RFIC designers to validate solutions.

Skills

Python programming

Machine learning

PyTorch

TensorFlow

scikit-learn

Data structures & algorithms

Object-oriented programming

Analytical thinking

Education

Master's or PhD in EE / CE / CS / EDA/CAD / Applied Mathematics

Tools

Git

Linux

Windows

Job description

Keysight EDA is seeking an AI/ML Layout Engineering Intern to help automate RFIC and analog layout generation. You will work with EDA engineers, AI researchers, and RFIC domain experts to build intelligent workflows that boost designer productivity and accelerate chip development.

The role emphasizes Python and possibly C++ development, with exposure to ML frameworks and design automation concepts in a collaborative, Agile setting. Relocation is available for California candidates.