Senior R&D Engineer – AI-Driven Layout Synthesis, PCells & Design Optimization

Anite; Calabasas (CA); On-site; USD 129,000 - 216,000; Full time

Benefits offered by this job

Medical, dental and vision

Health Savings Account

401(k) Plan

Flexible Time Off

Job summary

Keysight is seeking an R&D Engineer to advance RFIC layout automation for RFIC, analog and microwave design applications. You will work on parameterized cell development, lattice generation, and machine learning-enabled optimization to accelerate semiconductor productivity.

The role requires strong RFIC/analog experience, proficiency in Python/C++, and collaboration with RFIC designers and software engineers to deliver scalable EDA capabilities in a production environment.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, or related discipline.
• Strong hands-on experience in RFIC, analog, microwave, or mixed-signal design.
• Deep expertise in layout automation, parameterized layout generation, and PCell development.
• Strong understanding of semiconductor layout methodologies, design rules, physical verification, and EM-aware design practices.
• Experience developing software using Python and/or C++.
• Strong understanding of computational geometry, algorithms, and software architecture.
• Experience with circuit simulation, optimization workflows, and semiconductor design automation tools.
• Proven problem-solving and analytical skills with the ability to translate complex engineering workflows into scalable automation solutions.

Responsibilities

• Develop advanced PCells, Python-based cells, and automated layout generation capabilities for RFIC, microwave, and analog components.
• Design and implement layout automation solutions including geometry generation, placement, routing, symmetry enforcement, design-rule-aware synthesis, and EM-aware design flows.
• Integrate layout automation with circuit and EM simulation environments to enable automated design optimization, parameter exploration, and design-space analysis.
• Develop intelligent optimization frameworks leveraging machine learning, surrogate modeling, Bayesian optimization, and reinforcement learning techniques to accelerate design convergence.
• Build scalable software solutions in Python and C++ that support next-generation AI-assisted semiconductor design workflows.
• Collaborate with RFIC designers, modeling experts, and software engineers to deliver production-quality EDA capabilities that improve design productivity and product performance.

Skills

RFIC design

Analog/microwave

PCell development

Python

C++

EM-aware design

Design rules

Machine learning for design

Education

MS or PhD in Electrical/Computer Engineering or related

Tools

Cadence Virtuoso

Job description

Overview

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Overview

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

We are seeking a highly skilled R&D Engineer to develop next-generation layout automation technologies for RFIC, analog, and microwave design applications. This role combines deep expertise in parameterized cell (PCell) development, RFIC layout generation, circuit simulation, design optimization, and machine learning to accelerate semiconductor design productivity. The successful candidate will contribute to intelligent design automation workflows spanning layout synthesis, simulation-driven optimization, surrogate modeling, and AI-assisted design generation.

Responsibilities

• Develop advanced PCells, Python-based cells, and automated layout generation capabilities for RFIC, microwave, and analog components.
• Design and implement layout automation solutions including geometry generation, placement, routing, symmetry enforcement, design-rule-aware synthesis, and EM-aware design flows.
• Integrate layout automation with circuit and EM simulation environments to enable automated design optimization, parameter exploration, and design-space analysis.
• Develop intelligent optimization frameworks leveraging machine learning, surrogate modeling, Bayesian optimization, and reinforcement learning techniques to accelerate design convergence.
• Build scalable software solutions in Python and C++ that support next-generation AI-assisted semiconductor design workflows.
• Collaborate with RFIC designers, modeling experts, and software engineers to deliver production-quality EDA capabilities that improve design productivity and product performance.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, or related discipline.
• Strong hands-on experience in RFIC, analog, microwave, or mixed-signal design.
• Deep expertise in layout automation, parameterized layout generation, and PCell development.
• Strong understanding of semiconductor layout methodologies, design rules, physical verification, and EM-aware design practices.
• Experience developing software using Python and/or C++.
• Strong understanding of computational geometry, algorithms, and software architecture.
• Experience with circuit simulation, optimization workflows, and semiconductor design automation tools.
• Proven problem-solving and analytical skills with the ability to translate complex engineering workflows into scalable automation solutions.

Preferred Qualifications

• Experience with RFIC passive and active component design including inductors, transformers, transmission lines, filters, matching networks, mixers, and power amplifiers.
• Experience with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn.
• Knowledge of surrogate modeling, design-space exploration, Bayesian optimization, and reinforcement learning.
• Familiarity with ADS, Cadence Virtuoso, EM simulation tools, or related EDA platforms.
• Experience building AI-assisted engineering applications and intelligent automation workflows.
• Experience working in Agile software development environments.

The level of role will be based on applicable experience, education and skills; Most offers will be between the minimum and the midpoint of the Salary Range listed below.

CA pay range: MIN $129,450- MAX $215,740

Note:

For other locations, pay ranges will vary by region

This role is eligible for our Keysight Results Bonus Program

US Employees May Be Eligible For The Following Benefits

• Medical, dental and vision
• Health Savings Account
• Health Care and Dependent Care Flexible Spending Accounts
• Life, Accident, Disability insurance
• Business Travel Accident and Business Travel Health
• 401(k) Plan
• Flexible Time Off, Paid Holidays
• Paid Family Leave
• Discounts, Perks
• Tuition Reimbursement
• Adoption Assistance
• ESPP (Employee Stock Purchase Plan)
• Restricted Stock Units

Careers Privacy Statement

Keysight is an Equal Opportunity Employer

Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.