Senior AI ASIC Physical Design Lead with Equity

Acceler8 Talent; Mountain View (CA); Hybrid; USD 210,000 - 260,000; Full time

Benefits offered by this job

Equity participation

Medical coverage

Dental coverage

Vision coverage

401(k)

Paid time off

Job summary

Acceler8 Talent is seeking a Principal Physical Design Engineer to own the physical implementation of high-performance ASIC blocks within a next-generation AI accelerator.

You will work from floorplanning through tapeout, partnering with architects, RTL, verification, and software teams to optimize performance, power, and area while collaborating with foundries and EDA vendors to deliver production-ready silicon.

Qualifications

• 8+ years of experience in physical design for complex, high-performance ASICs at 7nm or below.
• Hands-on expertise across the full implementation flow: synthesis, P&R, CTS, timing closure, signoff.
• Experience with industry-standard signoff tools (PrimeTime, Tempus).

Responsibilities

• Own the complete physical design flow for major SoC blocks from floorplanning to final signoff.
• Develop AI-assisted implementation methodologies to improve design productivity.
• Drive place and route, clock tree synthesis, timing closure, power optimization, and physical verification.
• Collaborate with architecture, RTL, verification, and software teams to optimize implementation for performance, power, and area.
• Partner with foundries and EDA vendors to resolve implementation challenges and deliver production-ready silicon.

Skills

Physical design expertise

Synthesis/Place & Route

Clock tree synthesis

Power/area optimization

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

Job description

Acceler8 Talent is seeking a Principal Physical Design Engineer to own the physical implementation of high-performance ASIC blocks within a next-generation AI accelerator.

You will work from floorplanning through tapeout, partnering with architects, RTL, verification, and software teams to optimize performance, power, and area while collaborating with foundries and EDA vendors to deliver production-ready silicon.