Physical Design Engineer, AI Accelerator — Equity

River AI Inc.; Palo Alto, Austin (CA, TX); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, vision benefits

Unlimited PTO

Relocation support

Job summary

River AI Inc. is seeking exceptional physical design engineers to transform architectural concepts into production-ready silicon. You will own the physical flow from synthesis through tape-out, ensuring timing, power, and area targets on advanced nodes.

You will collaborate with RTL teams, optimize layouts for high-density compute blocks, and advance AI accelerator implementations using next-gen EDA flows. Austin or Palo Alto-based role with visa sponsorship available.

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering; 5+ years of experience with advanced process nodes (7nm or below).
• Proficiency with physical design, timing, and sign-off tools (Innovus, Fusion Compiler, PrimeTime, RedHawk).
• Experience in logic synthesis, memory macros, and multi-voltage design using UPF/CPF.

Responsibilities

• Own the physical implementation flow from RTL synthesis through placement, CTS, and routing for high-performance blocks.
• Maximize cell density and PDN robustness to meet aggressive frequency targets on advanced nodes.
• Conduct STA, fix setup/hold violations, and resolve SI/EM/IR-drop constraints across clock domains.
• Run and debug Design Rule Checking (DRC), LVS, and Antenna checks; ensure sign-off readiness.
• Co-design with RTL/architecture teams to provide early physical feedback and improve routing closure.

Skills

Synthesis & P&R

PPA optimization

STA & verification

Physical design flow

RTL co-design

Automation scripting

Education

Electrical Engineering / Computer Engineering

5+ years industry experience

Tools

Innovus

Fusion Compiler

PrimeTime

RedHawk

Job description

River AI Inc. is seeking exceptional physical design engineers to transform architectural concepts into production-ready silicon. You will own the physical flow from synthesis through tape-out, ensuring timing, power, and area targets on advanced nodes.

You will collaborate with RTL teams, optimize layouts for high-density compute blocks, and advance AI accelerator implementations using next-gen EDA flows. Austin or Palo Alto-based role with visa sponsorship available.