ASIC Security Design & Integration Engineer

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 185,000 - 325,000; Full time

Job summary

Apple Inc. in Cupertino is seeking an ASIC Design and Integration Engineer to build secure subsystems for the Apple SoC.

You will design the state-of-the-art hardware defenses that prevent side-channel attacks and protect customer data across Apple's product line. Responsibilities include architecting and integrating security features, ensuring timing, performance, and security requirements, and driving RTL-to-netlist flows with Lint, CDC/RDC analysis, UPF development, timing and synthesis.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering and 10 years of industry experience.
• 10 years RTL design experience with Verilog or SystemVerilog.

Responsibilities

• Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time
• Integrating security IPs into secure subsystem and ensuring timing, performance and security requirements are met
• Resolving integration issues across multiple IP blocks and coordinating with IP owners on interface and functionality concerns
• Driving front-end quality flows from RTL to netlist, including hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis.
• Leveraging AI-assisted tools to enhance design quality and productivity.

Skills

RTL design

Verilog

SystemVerilog

CDC/RDC analysis

UPF

low-power design

timing analysis

cryptography

AMBA AXI

AMBA AHB

AMBA APB

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Job description

Apple Inc. in Cupertino is seeking an ASIC Design and Integration Engineer to build secure subsystems for the Apple SoC.

You will design the state-of-the-art hardware defenses that prevent side-channel attacks and protect customer data across Apple's product line. Responsibilities include architecting and integrating security features, ensuring timing, performance, and security requirements, and driving RTL-to-netlist flows with Lint, CDC/RDC analysis, UPF development, timing and synthesis.