SDE II: High-Speed Interconnect Validation for AI Chips

Amazon; Austin (TX); On-site; USD 144,000 - 194,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Job summary

Annapurna Labs, an AWS organization, seeks a Post-Silicon Validation engineer to validate high-speed interfaces (HBM, PCIe, UCIe) and ensure link integrity across production cycles. You will work in the lab, performing eye diagrams, jitter analysis, and protocol tests, driving data-driven readiness for next-gen ML accelerators.

You will collaborate with PHY teams, optimize equalization, and stress-test links across PVT conditions, delivering robust validation outcomes for scalable AWS hardware.

Qualifications

• 3+ years of non-internship professional software development experience.
• 2+ years design or architecture (design patterns, reliability and scaling) of new and existing systems.
• Experience with RF measurement equipment: power meters, spectrum analyzers, vector signal generators, network analyzers, oscilloscopes.
• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering; or experience in test setup automation using MATLAB, Python, or Pearl.
• 3+ years of hands-on experience validating or characterizing at least one high-speed interface technology (HBM, PCIe, DDR, SerDes, or UCIe).
• Proficiency with signal integrity measurement techniques: eye diagram analysis, jitter decomposition, and voltage/timing margin assessment.
• Familiarity with at least one interface specification standard (JEDEC HBM/DDR, PCI-SIG PCIe, or UCIe consortium).

Responsibilities

• Validate high-speed interfaces (HBM, PCIe, UCIe, custom SerDes) end-to-end from PHY training through sustained traffic.
• Perform electrical characterization: eye diagrams, jitter analysis, voltage margin, and equalization tuning.
• Execute protocol-level compliance testing and interoperability validation against industry specifications.
• Stress-test links across PVT corners and aging conditions.
• Debug link training failures, bit errors, and performance degradation using lab instrumentation and silicon debug features.
• Collaborate with PHY design teams on equalization optimization, margin improvement, and silicon feedback.

Skills

Software development

Signal integrity

Python

MATLAB

Test automation

RF measurement equipment

Education

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering

Tools

MATLAB

Python

Pearl

Job description

Annapurna Labs, an AWS organization, seeks a Post-Silicon Validation engineer to validate high-speed interfaces (HBM, PCIe, UCIe) and ensure link integrity across production cycles. You will work in the lab, performing eye diagrams, jitter analysis, and protocol tests, driving data-driven readiness for next-gen ML accelerators.

You will collaborate with PHY teams, optimize equalization, and stress-test links across PVT conditions, delivering robust validation outcomes for scalable AWS hardware.