High-Speed IO Validation Engineer - PCIe/UALink & AI Servers

AMD; United States; Hybrid; USD 140,000 - 190,000; Full time

Job summary

AMD is seeking a High-Speed IO Validation Engineer in Santa Clara, CA, to validate and debug PCIe, UALink, Ethernet, and other high-speed interfaces across CPU and GPU platforms. You will work with PHY design, firmware, and platform teams to execute plans and drive root-cause analysis for silicon- and system-level issues.

Responsibilities include developing test automation, conducting characterization, and performing protocol-level debugging with lab equipment.

Qualifications

• 5+ years of experience in high-speed IO, silicon validation, system validation, or related areas.
• Experience with high-speed serial interfaces such as PCIe, CXL, Ethernet, UALink, or similar technologies.
• Strong understanding of signal integrity concepts, channel characteristics, equalization techniques (CTLE, DFE, TX FIR), and link-level behavior.
• Experience with lab bring-up, validation, and debug using high-speed measurement equipment such as oscilloscopes, BERTs, VNAs, and protocol analyzers.
• Strong programming and scripting skills in Python, C/C++, or similar languages for automation and data analysis.
• Familiarity with silicon bring-up, compliance testing, and system-level debug methodologies.
• Strong analytical and problem-solving skills with the ability to drive technical issues to resolution.
• Effective communication and collaboration skills within cross-functional engineering teams.

Responsibilities

• Execute validation plans for high-speed IO interfaces across CPU and GPU platforms.
• Support post-silicon bring-up, characterization, compliance testing, margining, and interoperability validation across platforms.
• Collaborate with design, architecture, firmware, board, and test teams to investigate and resolve high-speed interface issues.
• Develop and enhance test automation, validation scripts, and data analysis tools to improve validation efficiency and coverage.
• Perform electrical- and protocol-level debug using oscilloscopes, BERTs, protocol analyzers, and other lab equipment.
• Analyze signal integrity and power integrity and drive corrective actions based on results.
• Document validation findings, debug results, and recommendations for stakeholders.
• Contribute to improving validation methodologies and lab infrastructure.

Skills

High-speed IO

Silicon validation

System validation

Python

C/C++

Analytical skills

Communication skills

Education

Electrical/Computer Engineering degree

Tools

Oscilloscopes

BERTs

VNAs

Protocol analyzers

Job description

AMD is seeking a High-Speed IO Validation Engineer in Santa Clara, CA, to validate and debug PCIe, UALink, Ethernet, and other high-speed interfaces across CPU and GPU platforms. You will work with PHY design, firmware, and platform teams to execute plans and drive root-cause analysis for silicon- and system-level issues.

Responsibilities include developing test automation, conducting characterization, and performing protocol-level debugging with lab equipment.