Satellite Hardware Engineer

GCS Recruitment; Redmond (WA); On-site; USD 130,000 - 190,000; Full time

Job summary

GCS Recruitment seeks a senior PCB designer to own high-speed board development within a phased-array signal chain. You will drive schematic capture, component selection, and 20+ layer layouts, bringing boards from design into lab bring-up.

You’ll validate multi-gigabit interfaces (SerDes, PCIe, DDR), architect power delivery for dense boards, and run bench debugging with scopes and probes, ensuring designs meet reliability and radiation considerations. U.S.

Qualifications

• Experience designing high-complexity, high-speed boards with precise impedance control.
• Hands-on bench debugging and root-cause analysis on lab-scale hardware.
• Experience with distributed teams and parallel design/validation workflows.

Responsibilities

• Design high-complexity, high-speed digital boards: schematic capture, component selection, and layout ownership on 20+ layer, thousands-of-components designs built around custom silicon.
• Architect power delivery for boards carrying hundreds of high-performance chips—rail generation, sequencing, budgeting, and protection.
• Design and validate multi-gigabit interfaces (SerDes-class links, JESD204, PCIe, DDR) with SI/PI discipline.
• Bring up newly fabricated boards in the lab: first power-on, section-by-section checkout, root-cause debug with scopes and high-speed instruments.
• Run validation campaigns proving designs meet requirements, and feed findings into the next board revision.
• Select components with reliability, thermal, vibration, and radiation considerations in partnership with specialist teams.

Skills

Board design ownership

SerDes PCIe DDR

Power delivery

Lab debugging

Citizenship required

Tools

Siemens Xpedition

Altium

Cadence Allegro

Oscilloscopes

Job description

THE ROLE

You will own complex, high-speed board design in the phased-array signal chain - and see your designs through the lab. The team runs design and validation in parallel: while one board revision is being validated at the bench, the next is in design. You'll design boards (schematic capture, component selection, layout ownership), personally bring up newly fabricated hardware, debug to root cause, and feed findings into the next revision. This is a design-first seat with real lab ownership - not a test role, and not a documentation role.

WHAT YOU'LL DO

• Design high-complexity, high-speed digital boards: schematic capture, component selection, and layout ownership on 20+ layer, thousands-of-components designs built around custom silicon.

• Architect power delivery for boards carrying hundreds of high-performance chips - rail generation, sequencing, budgeting, and protection.

• Design and validate multi-gigabit interfaces (SerDes-class links, JESD204, PCIe, DDR) with disciplined signal- and power-integrity practice.

• Bring up newly fabricated boards in the lab: first power-on, section-by-section checkout, root-cause debug with oscilloscopes and high-speed instrumentation.

• Run validation campaigns proving designs meet requirements, and feed every finding into the next board revision.

• Select components with reliability, thermal, vibration, and radiation considerations in partnership with specialist review teams.

REQUIRED EXPERIENCE

• 8+ years of board-level design ownership - complex boards you can point to and say "mine": schematic, component selection, and layout.

• High-speed digital design: SerDes, JESD204, PCIe, and/or DDR, with hands-on signal-integrity practice (controlled impedance, length matching, stackup design).

• Power-architecture design for dense, high-power boards.

• Genuine lab fluency: you bring up and debug your own designs at the bench - scopes, analyzers, and methodical root-cause work.

• U.S. citizenship or permanent residency (export-controlled program - required).

NICE TO HAVE

• Space, aerospace, or defense high-reliability experience - DO-254/DO-160, MIL-STD, derating, worst-case analysis, radiation-aware design.

• Experience with Siemens Xpedition (Altium or Cadence Allegro equally welcome).

• Phased-array, radar, satellite, or other RF-system board experience (the boards, not the antennas).

• Experience working design/validation in parallel across board revisions.