Satellite Hardware Engineer - High-Speed Board Design

GCS Recruitment; Redmond (WA); On-site; USD 130,000 - 190,000; Full time

Job summary

GCS Recruitment seeks a senior PCB designer to own high-speed board development within a phased-array signal chain. You will drive schematic capture, component selection, and 20+ layer layouts, bringing boards from design into lab bring-up.

You’ll validate multi-gigabit interfaces (SerDes, PCIe, DDR), architect power delivery for dense boards, and run bench debugging with scopes and probes, ensuring designs meet reliability and radiation considerations. U.S.

Qualifications

• Experience designing high-complexity, high-speed boards with precise impedance control.
• Hands-on bench debugging and root-cause analysis on lab-scale hardware.
• Experience with distributed teams and parallel design/validation workflows.

Responsibilities

• Design high-complexity, high-speed digital boards: schematic capture, component selection, and layout ownership on 20+ layer, thousands-of-components designs built around custom silicon.
• Architect power delivery for boards carrying hundreds of high-performance chips—rail generation, sequencing, budgeting, and protection.
• Design and validate multi-gigabit interfaces (SerDes-class links, JESD204, PCIe, DDR) with SI/PI discipline.
• Bring up newly fabricated boards in the lab: first power-on, section-by-section checkout, root-cause debug with scopes and high-speed instruments.
• Run validation campaigns proving designs meet requirements, and feed findings into the next board revision.
• Select components with reliability, thermal, vibration, and radiation considerations in partnership with specialist teams.

Skills

Board design ownership

SerDes PCIe DDR

Power delivery

Lab debugging

Citizenship required

Tools

Siemens Xpedition

Altium

Cadence Allegro

Oscilloscopes

Job description

GCS Recruitment seeks a senior PCB designer to own high-speed board development within a phased-array signal chain. You will drive schematic capture, component selection, and 20+ layer layouts, bringing boards from design into lab bring-up.

You’ll validate multi-gigabit interfaces (SerDes, PCIe, DDR), architect power delivery for dense boards, and run bench debugging with scopes and probes, ensuring designs meet reliability and radiation considerations. U.S.