Digital Design Engineer

E-Space; Saratoga (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

A technology firm specialized in satellite avionics seeks a Digital Design Engineer for its Saratoga office. You will be responsible for the electrical design of complex digital boards for a next-generation satellite constellation, involving high-speed interfaces and FPGA integration. The ideal candidate has experience in satellite or spacecraft avionics design and is proficient with tools like Altium Designer and HyperLynx SI. A comprehensive compensation package of $150,000 - $250,000 is offered depending on experience.

Qualifications

• Experience with satellite or spacecraft avionics design.
• Familiarity with signal integrity simulation tools.
• Background in non-volatile memory technologies.

Responsibilities

• Own schematic design for digital avionics boards.
• Design high-speed SERDES interfaces.
• Drive board bring-up activities and verification.

Skills

High-speed SERDES interfaces

Clocking architectures

Radiation-tolerant design techniques

Collaboration with FPGA engineers

Power budgeting

Design reviews

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Altium Designer

HyperLynx SI

SPICE-based circuit simulation

Job description

E-Space is seeking experienced Digital Design Engineers for our Satellite Avionics team. The role involves owning the electrical design of complex digital boards for a next‑generation satellite constellation, including high‑speed interfaces, FPGA integration, and mixed‑signal subsystems. You will play a central role in delivering flight‑qualified avionics hardware from concept through qualification.

Key Responsibilities

• Own schematic design and component selection for digital avionics boards, from concept through flight qualification.
• Design high‑speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces with proper timing closure.
• Develop clocking architectures including PLL configuration, jitter management, and clock distribution networks.
• Perform power budgeting and system‑level power allocation across board subsystems.
• Apply radiation‑tolerant design techniques including SEU/SEE mitigation, TID considerations, and appropriate component derating.
• Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout requirements.
• Drive board bring‑up activities including configuration, interface verification, and structured debugging.
• Participate in design reviews and cross‑functional integration with RF, power, thermal, and mechanical teams.

Required Qualifications

• Own schematic design and component selection for digital avionics boards, from concept through flight qualification.
• Design high‑speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces with proper timing closure.
• Develop clocking architectures including PLL configuration, jitter management, and clock distribution networks.
• Perform power budgeting and system‑level power allocation across board subsystems.
• Apply radiation‑tolerant design techniques including SEU/SEE mitigation, TID considerations, and appropriate component derating.
• Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout requirements.
• Drive board bring‑up activities including configuration, interface verification, and structured debugging.
• Participate in design reviews and cross‑functional integration with RF, power, thermal, and mechanical teams.

Preferred Qualifications

• Experience with satellite or spacecraft avionics design and qualification (EM/QM/FM build cycles).
• Background in non‑volatile memory technologies (Flash, MRAM, FRAM) and in‑system programmability.
• Exposure to power supply design and power integrity analysis for digital boards.
• Experience with design for radiation reliability and single‑event effects mitigation at the board level.
• Familiarity with signal integrity simulation tools (HyperLynx SI/PI, Ansys, ADS).

Tools & Technologies

• Altium Designer (schematic capture and layout review)
• HyperLynx SI, SI/PI, and Full‑Wave (signal and power integrity)
• SPICE‑based circuit simulation
• FPGA vendor toolchains (for interface bring‑up and debug)

Compensation & Location

$150,000 - $250,000 a year.

This is a full‑time, exempt position based out of our Saratoga office. The total compensation package will be determined by experience and qualifications.