Senior Hardware Design Engineer

GCS Recruitment; Redmond (WA); On-site; USD 140,000 - 190,000; Full time

Job summary

GCS Recruitment is seeking a senior hardware engineer to own the design of complex, high-speed boards and lead lab bring-up for a phased-array signal chain. You will manage schematic capture, component selection, and layout ownership on very high-layer boards and oversee power delivery and multi-gigabit interface validation in a lab-focused role.

You will bring up boards at the bench, perform thorough fault isolation, and drive the next revision using findings from tests and measurements.

Qualifications

• 8+ years leading board-level design on complex boards
• Hands-on experience with high-speed digital design and signal integrity
• Experience with SerDes, PCIe, JESD204, DDR interfaces
• Ability to bring up hardware in lab and debug root causes
• U.S. citizenship or permanent residency required for export-controlled program

Responsibilities

• Own design of high-speed digital boards with 20+ layer stacks
• Architect power delivery for dense boards carrying many chips
• Design and validate high-speed interfaces (SerDes, PCIe, JESD204, DDR)
• Bring up fabricated boards in lab and perform bench debugging
• Run validation campaigns and feed findings into revisions
• Select components considering reliability, thermal, and radiation factors

Skills

Board-level design

High-speed digital

SerDes/PCIe

Power architecture

Lab bring-up

Tools

Oscilloscopes

Logic analyzers

High-speed instruments

Job description

THE ROLE

You will own complex, high-speed board design in the phased-array signal chain - and see your designs through the lab. The team runs design and validation in parallel: while one board revision is being validated at the bench, the next is in design. You'll design boards (schematic capture, component selection, layout ownership), personally bring up newly fabricated hardware, debug to root cause, and feed findings into the next revision. This is a design-first seat with real lab ownership - not a test role, and not a documentation role.

WHAT YOU'LL DO

• Design high-complexity, high-speed digital boards: schematic capture, component selection, and layout ownership on 20+ layer, thousands-of-components designs built around custom silicon.
• Architect power delivery for boards carrying hundreds of high-performance chips - rail generation, sequencing, budgeting, and protection.
• Design and validate multi-gigabit interfaces (SerDes-class links, JESD204, PCIe, DDR) with disciplined signal- and power-integrity practice.
• Bring up newly fabricated boards in the lab: first power-on, section-by-section checkout, root-cause debug with oscilloscopes and high-speed instrumentation.
• Run validation campaigns proving designs meet requirements, and feed every finding into the next board revision.
• Select components with reliability, thermal, vibration, and radiation considerations in partnership with specialist review teams.

REQUIRED EXPERIENCE

• 8+ years of board-level design ownership - complex boards you can point to and say "mine": schematic, component selection, and layout.
• High-speed digital design: SerDes, JESD204, PCIe, and/or DDR, with hands-on signal-integrity practice (controlled impedance, length matching, stackup design).
• Power-architecture design for dense, high-power boards.
• Genuine lab fluency: you bring up and debug your own designs at the bench - scopes, analyzers, and methodical root-cause work.
• U.S. citizenship or permanent residency (export-controlled program - required).