Digital Circuit Design Engineer

Apple Inc.; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Apple Inc. in Austin, Texas is seeking an experienced RTL verification engineer to validate design functionality, implement testbenches with SystemVerilog and UVM, and ensure compliance with architectural specs.

You will run and debug simulations, generate coverage analyses, and refine testbenches for reusable, scalable verification workflows across SRAMs, register files, and caches. Collaboration with circuit teams and use of industry tools are essential.

Qualifications

• RTL verification testbenches using SystemVerilog/Verilog.
• UVM-based verification environments with monitors and scoreboards.
• Verify memory blocks (SRAM, register files) and timing.
• Use Python/Perl/C++ to automate verification flows.
• Familiar with waveform tools for debugging.

Responsibilities

• Develop and maintain testbenches for RTL verification.
• Run simulations, triage failures, and track bugs.
• Analyze coverage and debug results to ensure high-quality verification.
• Refactor testbench code to improve reusability and maintainability.
• Collaborate with circuit designers and RTL teams across Apple Silicon projects.

Skills

SystemVerilog

Verilog

UVM

Python

Perl

C++

Regression testing

Waveform debugging

Timing analysis

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Verdi

Cadence Indago

Job description

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Ensure that all pre-silicon deliveries of custom IPs for Apple Socs are bug free. This involves working closely with circuit and RTL (Register Transfer Level) designers to validate design functionality, optimize performance, and ensure that the design complies with the architectural specifications. Review design and architectural specifications to understand use cases and corner conditions, then translate these into testbenches, including key verification components such as stimulus generation, checkers, assertions, and functional coverage, utilizing SystemVerilog and UVM (Universal Verification Methodology) which offers a more standardized and scalable verification approach. Ensure that the RTL/Verilog design files are bug free and match the specifications and requirements. Run and debug simulation regressions, triage failures, track bugs, and perform detailed coverage analysis to ensure high-quality verification results. Generate and analyze Toggle Coverage reports to verify complete signal toggling for each design. Leverage industry-standard tools such as Verdi and Cadence lndago for debugging simulation-waveforms, analyzing environment hierarchies, and bug resolution in complex verification environments. Develop and use Perl and Python-based automation scripts for automatic testbench generation and verification workflows, improving efficiency and reducing manual effort. Work with circuits pertaining to SRAMs, register files, and caches, applying academic knowledge in VLSI and circuit design to verify custom memory architectures. Refactor testbench code to enhance reusability and maintainability, eliminating hardcoded values and ensuring a modular verification environment. Use version control systems such as Perforce, documentation platforms like Confluence, and proprietary task management tools for effective cross-functional collaboration. 40 hours/week.

Minimum Qualifications

• Bachelor's degree or foreign equivalent in Computer Engineering, Electrical Engineering, or a related field.


• Experience and/or education must include:


• Utilizing SystemVerilog or Verilog to develop RTL verification testbenches for digital circuit designs, including simulation and analysis of design behavior.


• Utilizing Universal Verification Methodology (UVM) or equivalent methodology to develop verification environments, including monitors and scoreboards.


• Performing RTL design verification and debug using industry-standard waveform and simulation debug tools to identify functional failures and isolate root causes.


• Verifying digital memory and custom circuits (e.g., SRAM, register files, or other IP blocks), including read/write operations, timing behavior, and corner-case functionality.


• Utilizing formal verification tools, including Logical Equivalence Checking (LEC) or ESPCV or equivalent, to validate equivalence between RTL and synthesized netlists.


• Utilizing Python, Perl, or C++ to automate verification flows, regression execution, and test generation.


• Utilizing regression management and revision control systems to execute automated regression test suites and track changes across RTL and verification environments.


• Applying digital circuit fundamentals, including synchronous logic, finite state machines, timing analysis, and clock/reset behavior, to support design verification.

Preferred Qualifications

• N/A

This position is not subject to the application limits.

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