Senior Physical Design Engineer, Silicon

Google Inc.; Mountain View, Austin (CA, TX); On-site; USD 163,000 - 236,000; Full time

Job summary

Google Mountain View, CA, USA is seeking a Senior Physical Design Engineer for Silicon, with 8+ years in high-speed digital design and PPA optimization. The role involves owning block/IP physical design, solving timing via STA and physical verification, and coordinating with architecture and DFT teams.

Mountain View and Austin locations are mentioned, with in-person interviews likely. Applicants should have a Bachelor's degree in a related field; a Master's or PhD is preferred.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; equivalent practical experience.
• 8 years of experience with high-speed digital design, implementation, and PPA optimization.
• Experience with sign-off convergence domains, including STA, electrical checks, or physical verification.

Responsibilities

• Partner with architecture, RTL, and DFT teams to optimize power, performance, and area trade-offs.
• Own block and IP-level physical design implementations from synthesis through place and route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities, including static timing analysis, power recovery, and electrical layout checks.

Skills

High-speed digital design

PPA optimization

Static Timing Analysis (STA)

Electrical checks

Physical verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Job description

Senior Physical Design Engineer, Silicon

Google Mountain View, CA, USA ; Austin, TX, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Austin, TX, USA.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with high-speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
• Experience with sign-off convergence domains, including Static Timing Analysis (STA), electrical checks, or physical verification.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with advanced process nodes (e.g., 5nm, 3nm, 2nm, or below).
• Experience applying AI/ML-assisted techniques for physical design closure and PPA scaling.
• Proficiency in scripting (Python, Tcl, Perl) and data mining for QoR metrics.
• Understanding of EMIR flows, power grid design, and design reliability for high-frequency circuits.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

• Partner with architecture, RTL, and DFT teams to optimize power, performance, and area trade-offs.
• Own block and IP-level physical design implementations from synthesis through place and route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities, including static timing analysis, power recovery, and electrical layout checks.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.