Senior RTL Design Engineer, TPU Compute

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google Sunnyvale is seeking a Senior RTL Design Engineer to drive TPU Compute ASIC development, shaping AI/ML hardware acceleration and sophisticated RTL verification.

You will craft SystemVerilog RTL, design microarchitectures, and collaborate with cross-functional teams spanning software, architecture and physical design to achieve timing closure and performance goals.

Qualifications

• Bachelor's degree or equivalent practical experience in a relevant field.
• 8+ years of digital design experience using SystemVerilog RTL.
• Experience with power, performance and area optimizations.

Responsibilities

• Create and own microarchitecture for Compute accelerator IPs.
• Develop implement, and maintain design blocks or components.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with design verification and validation teams to create testplans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Skills

SystemVerilog RTL

Power optimization

Mentoring

Education

Bachelor's degree or equivalent in relevant field

Master's or PhD in EE/CE/CS with emphasis on computer architecture

Job description

Senior RTL Design Engineer, TPU Compute

Google

Sunnyvale, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital design using SystemVerilog RTL.
• Experience with power, performance and area optimizations.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience interacting with software, architecture, physical design and other cross-functional teams.
• Knowledge of processor design, accelerators, or memory hierarchies.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

You will be part of a team developing cutting-edge ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.

Responsibilities

• Create and own microarchitecture for Compute accelerator IPs.
• Develop implement, and maintain design blocks or components.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with design verification and validation teams to create testplans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

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