Research Engineer: AI for Chip Design & RL

Voltai; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Voltai is seeking engineers to post-train frontier models that autonomously handle complex semiconductor tasks. You will design RL environments, generate rich evaluation datasets, and partner with hardware and verification experts to define metrics and execution conditions.

You will craft reward functions, scaling strategies, and rigorous evaluation frameworks to push models toward reliable, efficient, and creative silicon reasoning in next-generation designs.

Qualifications

• Experience creating and scaling RL environments for LLMs or multimodal agents.
• Ability building evaluation datasets and benchmarks for complex reasoning or design tasks.
• Collaborating with hardware/verification experts to define evaluation metrics and conditions.
• Experience designing reward functions and feedback pipelines balancing correctness and efficiency.
• Conducting large-scale RL fine-tuning or post-training experiments for frontier models.

Responsibilities

• Post-train frontier models to autonomously perform complex tasks in semiconductor design and verification.
• Develop RL environments that simulate chip design workflows and verification steps.
• Create evaluation metrics, scaling strategies, and frameworks to improve model reliability and creativity in silicon reasoning.

Skills

RL environments

Evaluation datasets

Collaboration with hardware

Reward design

RL fine-tuning

Curriculum learning

Job description

Voltai is seeking engineers to post-train frontier models that autonomously handle complex semiconductor tasks. You will design RL environments, generate rich evaluation datasets, and partner with hardware and verification experts to define metrics and execution conditions.

You will craft reward functions, scaling strategies, and rigorous evaluation frameworks to push models toward reliable, efficient, and creative silicon reasoning in next-generation designs.