RTL Design Engineer

YOH Services LLC; Santa Clara (CA); On-site; USD 125,000 - 150,000; Full time

Job summary

An innovative company is looking for a talented RTL Design Engineer to join their dynamic team. In this role, you will support the design of cutting-edge SoCs that drive advancements in machine learning technology. With a focus on RISC-V architectures, you will leverage your extensive RTL design experience to tackle complex challenges and contribute to the development of high-performance computing solutions. This position offers a chance to work in a collaborative environment where your expertise will directly impact groundbreaking projects. If you're passionate about technology and eager to make a difference, this opportunity is for you.

Qualifications

• 7+ years of RTL design experience with strong debugging skills.
• Experience with RISC-V architectures and machine learning accelerators.

Responsibilities

• Support RTL design for SoCs focused on machine learning accelerators.
• Debug RTL/logic issues in pre-silicon and post-silicon environments.

Skills

RTL Design

Verilog

Debugging RTL/Logic Issues

Verification Flows

SoCs for Machine Learning

Education

Degree in Electrical Engineering

Degree in Computer Engineering

Degree in Computer Science

Tools

GIT

BENDER

Job description

RTL Design Engineer

Category: Engineering

Employment Type: Contract

Reference: BH-380128-1

Job Description

We are seeking a skilled RTL Design Engineer with a strong background in supporting RISC-V architectures. The primary focus will be on SoCs built around Machine Learning accelerators. The ideal candidate should have solid RTL design experience, an understanding of verification flows, and the ability to provide consistent support with minimal supervision.

Required Qualifications

• 7+ years of RTL design experience
• Proficiency in Verilog
• Ability to debug RTL/logic issues across various hierarchies in pre-silicon and post-silicon environments (pre-silicon focus)
• Experience developing RTL and understanding verification flows
• Knowledge of SoCs built around machine learning accelerators
• Experience with companies such as Groq, Nvidia, AMD, or Intel

Preferred Qualifications

• RISC-V experience
• Degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields with at least 5 years of industry experience
• Experience with GIT/BENDER
• Strong background in high-performance Out-of-Order CPU microarchitecture
• Experience working with x86, ARM, or RISC-V CPUs
• Understanding of CPU architecture components like Rename, Scheduler, Reorder Buffer, and Datapath

Compensation

Estimated minimum rate: $70.00
Estimated maximum rate: $90.00

Note: Pay ranges are estimates; actual compensation depends on experience and qualifications. All qualified applicants are encouraged to apply.

Equal Opportunity Employment

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. We consider all qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.

For accommodations, visit https://www.yoh.com/applicants-with-disabilities.

California applicants: Qualified individuals with arrest or conviction records will be considered under applicable laws.