ASIC/RTL Design Engineer - Specialized (US)

Tech Providers,; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

An established industry player is seeking a skilled ASIC/RTL Design Engineer to join their dynamic team in Santa Clara. This role involves developing and maintaining tests for functional verification, collaborating with architects and engineers to ensure robust design verification. The ideal candidate will have over 10 years of experience in ASIC design verification, proficiency in C/C++, Verilog, and SystemVerilog, and a knack for debugging firmware and RTL code. Join a forward-thinking company and contribute to cutting-edge IP development in a collaborative environment.

Qualifications

• 10+ years of ASIC design verification experience required.
• Proficient in debugging firmware and RTL code using simulation tools.

Responsibilities

• Develop and maintain tests for functional verification.
• Build directed and random verification tests and debug failures.

Skills

C/C++

Verilog

SystemVerilog

UVM

Python

Perl

TCL

Debugging Firmware

ASIC Design Verification

Job description

Job Title: ASIC/RTL Design Engineer - Specialized

Duration: 12+ months

Job location: Santa Clara, CA (Onsite)

The Role:

• We are looking for an adaptive, self-motivated Design Verification Engineer to join our growing team.
• Be a part of a team that delivers industry-leading IP and helps our experts in RTL, firmware, circuit, and architecture teams develop leading-edge and differentiating IPs.

Key Responsibilities:

• Develop and maintain tests for functional verification.
• Build directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects, and correct any test issues.
• Work on functional and code coverage verification.
• Provide technical support to other teams.

Preferred Experience:

• Experience with C/C++
• Experience with Verilog, SystemVerilog, and modern verification libraries like UVM
• 10+ years of ASIC design verification experience
• Experience or background with DDR or Memory Controller; PHY Verification is a plus
• Experience with scripting languages like Python, Perl, and TCL is a plus
• Ability to collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified
• Understanding of Design for Test methodologies and DFT verification experience is a plus
• Proficient in debugging firmware and RTL code using simulation tools