RTL Design Engineer-Specialized

ZipRecruiter; Santa Clara (CA); On-site; USD 125,000 - 150,000; Full time

Job summary

An innovative firm is seeking a principal level RTL Design Engineer to join their dynamic team in Santa Clara. This role offers the opportunity to work on cutting-edge I/O SoCs, contributing to the design and development of critical components. Candidates will engage with advanced technologies including Gbit SERDES and high frequency designs, ensuring their expertise shapes the future of integrated circuit design. If you're passionate about pushing the boundaries of technology and thrive in a collaborative environment, this position is perfect for you.

Qualifications

• Principal level RTL design engineer with experience in Gbit SERDES and high frequency design.
• Contribute to all aspects of SoC design including subsystem definition.

Responsibilities

• Participate in the design of leading edge I/O SoCs.
• Develop micro-architectural specifications and perform module level verification.

Skills

RTL Design

High Frequency Design

SoC Design

Micro-architectural Specifications

Module Level Verification

Lint & CDC

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Job description

We are looking for RTL Design Engineer Specialized for our client in Santa Clara, CA.

Job Title: RTL Design Engineer Specialized

Job Location: Santa Clara, CA

Job Type: Contract

Pay Range: $86.20/hr - $103.44/hr

Job Description:

• This is a position for principal level RTL design engineer. As a part of the design team, candidates will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design.
• Successful candidates will be participating in the design of leading edge I/O SoCs.
• RTL Design Engineers are expected to contribute in all aspects of SoC design including subsystem definition.
• Development of micro-architectural specifications, strong RTL design, module level verification, Lint & CDC.
• Having experience in Gbit high frequency design such as PCIe & Ethernet Phy design is a big plus.
• Candidates must have a BS in EE or CS. MS is a plus.