RTL Design Engineer

Yoh, A Day & Zimmermann Company; Santa Clara (CA); On-site; USD 125,000 - 150,000; Full time

Job summary

An innovative firm is on the lookout for a talented RTL Design Engineer who excels in supporting RISC-V architectures. This role involves working on cutting-edge SoCs focused on machine learning accelerators, where you'll leverage your extensive RTL design experience and proficiency in Verilog. As a key player in the team, you will independently tackle RTL/logic debugging across various hierarchies, ensuring high performance and reliability. Join a forward-thinking company that values expertise and offers an exciting opportunity to impact the future of technology.

Qualifications

• 7+ years of RTL design experience required.
• Proficiency in Verilog and debugging RTL/logic issues is essential.

Responsibilities

• Support RISC-V architectures and machine learning accelerators.
• Provide consistent support with minimal supervision.

Skills

RTL Design

Verilog

Debugging RTL/logic issues

RTL development and verification flows

Understanding of SoCs

RISC-V experience

Education

Degree in Electrical Engineering

Degree in Computer Science

Tools

GIT

BENDER

Job description

Job Description

RTL Design Engineer

We are seeking a skilled RTL Design Engineer with a strong background in supporting RISC-V architectures. The primary focus will be on SoCs built around Machine Learning accelerators. The ideal candidate should have solid RTL design experience and a good understanding of verification flows. The role requires an independent engineer capable of providing consistent support with minimal supervision.

Requirements:

1. 7+ years of RTL design experience.
2. Proficiency in Verilog.
3. Ability to debug RTL/logic issues across various hierarchies (core, chip) in pre-silicon and post-silicon environments, with a focus on pre-silicon.
4. Experience in RTL development and verification flows.
5. Understanding of SoCs built around machine learning accelerators.
6. Experience with companies like Groq, Nvidia, AMD, possibly Intel, etc.

Preferred Skills:

• RISC-V experience.
• Degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, Computer Science, or related fields, with at least 5 years of industry experience.
• Experience with GIT/BENDER.
• Strong background in high-performance Out-of-Order CPU microarchitecture.
• Experience working with x86, ARM, or RISC-V CPUs.
• Knowledge of CPU architecture components such as Rename, Scheduler, Reorder Buffer, and Datapath for Out-of-Order CPUs.

Compensation:

Estimated minimum rate: $70.00/hour

Estimated maximum rate: $90.00/hour

Note: Pay ranges are estimates. Actual compensation will depend on experience, expertise, and qualifications. All qualified applicants are encouraged to apply.

Equal Opportunity Employer:

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. We consider all qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.

For accommodations during the application process, contact us at https://www.yoh.com/applicants-with-disabilities.

For California applicants, employment considerations include the Los Angeles County Fair Chance Ordinance and the California Fair Chance Act, which address criminal history disclosures.

About Yoh:

Founded in 1940, Yoh operates from 75 locations across North America and is headquartered in Philadelphia, PA. As the first technology staffing firm in the nation and a part of Day & Zimmermann, Yoh has a global presence with over 150 locations worldwide.

Company Website: https://www.yoh.com/