RL-Driven Chip Design Research Engineer

Anthropic Limited; San Francisco (CA); Hybrid; USD 500,000 - 850,000; Full time

Benefits offered by this job

Competitive compensation

Equity donation matching

Generous vacation

Parental leave

Flexible working hours

Office in San Francisco

Job summary

Anthropic is hiring a Research Engineer for the Code RL team to advance silicon design with reinforcement learning-focused environments and evaluations. You will work on RTL generation, formal verification, and physical design optimization, collaborating across research and production to scale innovations.

Ideal candidates have ASIC/FPGA experience, strong RTL/verification skills, and fluency with EDA tools.

Qualifications

• Expertise in ASIC/FPGA design including RTL, verification (UVM, formal), physical design (synthesis, PnR, timing), PPA optimization, DFT and ECOs.
• Fluent with industry EDA tools and processes.
• Have taped out chips and experience going from spec to silicon.

Responsibilities

• Invent, design, and implement RL environments for agentic RTL generation and verification.
• Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape our roadmap.
• Deliver your work into research and production training runs.
• Collaborate with other researchers and engineers across and outside Anthropic.

Skills

ASIC design

FPGA design

RTL

Design verification

UVM

Formal methods

Physical design

Synthesis

Place-and-route

Timing closure

PPA optimization

DFT

ECOs

Education

Bachelor's degree in a relevant field

Tools

EDA tools

Architecture simulators

High-level synthesis

Job description

Anthropic is hiring a Research Engineer for the Code RL team to advance silicon design with reinforcement learning-focused environments and evaluations. You will work on RTL generation, formal verification, and physical design optimization, collaborating across research and production to scale innovations.

Ideal candidates have ASIC/FPGA experience, strong RTL/verification skills, and fluency with EDA tools.