Staff ML Research Engineer - RL for Chip Design (Equity)

Architect Labs; Palo Alto (CA); On-site; USD 190,000 - 260,000; Full time

Benefits offered by this job

Competitive salary

Meaningful equity stake

Job summary

Architect is a frontier AI lab focused on custom silicon and AI workloads. As a Member of the Technical Staff, you will help train AI models for chip design, verification and exploration, with productionization on leading foundry tech like TSMC.

You will co-design RL environments, implement reward models, and scale post-training techniques while collaborating across research and production teams to deliver reliable, high-performance systems.

Qualifications

• PhD or strong research-backed MS/BS in a relevant field.
• Deep RL expertise with deployment experience.
• End-to-end ML pipelines and model fine-tuning experience.
• Experience with large-scale distributed systems and HPC.
• Ability to balance research with engineering rigor and reliability.

Responsibilities

• Co-design and implement RL environments and reward models.
• Work at intersection of research and production for chip designs.
• Build and run robust pipelines for model fine-tuning and evaluation.
• Own end-to-end RL workflow: reward modeling to test-time optimization.
• Collaborate with researchers to translate techniques into production.

Skills

Reinforcement learning

Post-training ML

End-to-end ML pipelines

Distributed systems

PyTorch/CUDA

Model evaluation

Education

PhD in CS/EE or related

BS/MS with strong research background

Tools

PyTorch

CUDA

LoRA/QLoRA

Distributed training

Job description

Architect is a frontier AI lab focused on custom silicon and AI workloads. As a Member of the Technical Staff, you will help train AI models for chip design, verification and exploration, with productionization on leading foundry tech like TSMC.

You will co-design RL environments, implement reward models, and scale post-training techniques while collaborating across research and production teams to deliver reliable, high-performance systems.