Research Engineer, Chip Design RL

Anysilicon; San Francisco (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Anthropic is seeking a Research Engineer to enhance models' abilities in hardware design, focusing on silicon design and RL-environment development. The role involves RTL generation and verification, physical design optimization, and formal verification, with emphasis on integrating research into production training runs.

Candidates should have a bachelor’s degree or equivalent, expertise in ASIC/FPGA design, and fluency with industry EDA tools.

Qualifications

• Bachelor’s degree or equivalent in a relevant field.
• Expertise in ASIC or FPGA design, including RTL and design verification.
• Experience with physical design processes such as synthesis and timing closure.
• Fluency with industry EDA tools and processes.
• Experience in chip design from specification to silicon.

Responsibilities

• Invent, design, and implement RL environments for RTL generation and verification.
• Optimize physical design and conduct formal verification.
• Work on EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape the research roadmap.
• Deliver work into research and production training runs.
• Collaborate with researchers and engineers across Anthropic.

Skills

Reinforcement learning

ML accelerators

Architecture simulators

Education

Bachelor’s degree or equivalent in a relevant field

Tools

EDA tools

ASIC/FPGA tooling

RTL design

Job description

Anthropic is dedicated to creating reliable, interpretable, and steerable AI systems that are safe and beneficial for users and society. The Reinforcement Learning (RL) teams at Anthropic play a pivotal role in advancing AI systems, contributing to the Claude models and focusing on areas such as effective computer usage, code generation, RL research for large language models, scalable infrastructure, and enhanced reasoning capabilities. The Code RL team is seeking a Research Engineer to enhance models' abilities in hardware design, particularly in silicon design.

Responsibilities:

• Invent, design, and implement RL environments for RTL generation and verification.
• Optimize physical design and conduct formal verification.
• Work on EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape the research roadmap.
• Deliver work into research and production training runs.
• Collaborate with researchers and engineers across Anthropic.

Qualifications:

• Bachelor’s degree or equivalent in a relevant field.
• Expertise in ASIC or FPGA design, including RTL and design verification.
• Experience with physical design processes such as synthesis and timing closure.
• Fluency with industry EDA tools and processes.
• Experience in chip design from specification to silicon.

Skills:

• Knowledge of reinforcement learning and its applications.
• Experience with ML accelerators or high-performance compute hardware.
• Familiarity with high-level synthesis or architecture simulators.
• Ability to balance research exploration with engineering implementation.