RISC-V Post-Silicon Validation Engineer

Tenstorrent University Jobs; Santa Clara (CA); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Post‑Silicon Validation Engineer to drive bring‑up, validation, and debugging of RISC‑V based SoCs. The role sits at the intersection of silicon, firmware, and system software, requiring hands‑on lab experience and deep understanding of SoC architectures.

The position is hybrid, based out of Austin TX or Santa Clara CA, with opportunities at various experience levels and compensation aligned with the level and location.

Qualifications

• 5+ years of post‑silicon validation, bring‑up, and silicon debug experience.
• Strong grasp of CPU/SoC architectures including RISC‑V privilege modes, caches, and memory systems.
• Ability to debug complex hardware/software interaction issues using lab tools and low‑level software.
• Experience working with RTL, firmware, and software teams in cross‑functional environments.

Responsibilities

• Lead first‑silicon bring‑up of RISC‑V CPU–based SoCs and execute post‑silicon validation plans.
• Debug silicon issues across cores, interconnects, memory subsystems, peripherals, and high‑speed interfaces.
• Develop and debug bare‑metal tests, boot flows, and validate Linux bring‑up and drivers.
• Provide actionable feedback and drive fixes for future silicon revisions.

Skills

SoC bring‑up

RISC‑V

Debug hardware

Cross‑functional collaboration

Job description

Tenstorrent is seeking a Post‑Silicon Validation Engineer to drive bring‑up, validation, and debugging of RISC‑V based SoCs. The role sits at the intersection of silicon, firmware, and system software, requiring hands‑on lab experience and deep understanding of SoC architectures.

The position is hybrid, based out of Austin TX or Santa Clara CA, with opportunities at various experience levels and compensation aligned with the level and location.