RISC-V Microarchitecture & RTL Design Engineer (AI‑Assisted)

Mirafra Technologies; Santa Clara (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Mirafra Technologies is seeking engineers to define and develop RISC-V CPU unit microarchitecture specifications, covering branch predictors, rename, instruction scheduling, vector execution, and load/store paths. The role includes RTL design quality, verification environment refinement, and PPA closure.

You will also leverage AI tools to accelerate CPU design and may mentor junior engineers based on seniority.

Qualifications

• Define and develop microarchitecture specifications for RISC-V CPU units.
• Responsible for RTL quality including design verification and PPA closure.
• Use AI tools to accelerate CPU design process.
• Mentor junior engineers as required.

Responsibilities

• Define and develop microarchitecture specifications for RISC-V CPU units.
• Responsible for RTL quality including design verification and PPA closure.
• Use AI tools to accelerate CPU design process.
• Mentor junior engineers as required.

Skills

Microarchitecture specifications

RTL Design

Verification

PPA closure

AI tools usage

Mentoring

Job description

Mirafra Technologies is seeking engineers to define and develop RISC-V CPU unit microarchitecture specifications, covering branch predictors, rename, instruction scheduling, vector execution, and load/store paths. The role includes RTL design quality, verification environment refinement, and PPA closure.

You will also leverage AI tools to accelerate CPU design and may mentor junior engineers based on seniority.