Senior Principal AI/ML CPU Architect - RISC-V Vector Core

GlobalFoundries; California (MO); On-site; USD 171,000 - 325,000; Full time

Job summary

GlobalFoundries seeks an experienced CPU IP Design Engineer to lead RTL development of a high-performance AI-enabled RISC-V CPU core. You will drive micro-architecture, design critical blocks, and collaborate with modeling teams to optimize performance, power, and area.

The role covers verification strategy, design features refinement, and integration at the SoC level, requiring deep expertise in Verilog/SystemVerilog and vector/matrix CPU engines.

Qualifications

• Master’s with 10+ years of experience, PhD 5+ years of work experience.
• Hands-on knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core.
• Expertise in instruction fetch/decode, branch prediction, scheduling, ROB, out-of-order execution and vector/memory subsystems.

Responsibilities

• Drive the micro-architecture and design of critical blocks of the CPU core.
• Design of RISC-V Vector CPU core and its custom extensions.
• Design of AI-enabled Matrix engine to augment the Vector CPU.
• Explore high-performance strategies with the CPU modeling team.
• Configure RTL design features to meet power, performance, area, timing goals.
• Support functional verification and assist verification strategy.
• Assist with RTL performance verification and timing/power optimization.

Skills

CPU architecture

RISC-V

Vector CPU

Verilog/SystemVerilog

RTL design

Performance optimization

Python/Perl scripting

Digital design

Verification

Education

Master's degree in EE/CS

PhD (optional)

Tools

Verilog simulators

Waveform debugging tools

SoC integration tools

Job description

GlobalFoundries seeks an experienced CPU IP Design Engineer to lead RTL development of a high-performance AI-enabled RISC-V CPU core. You will drive micro-architecture, design critical blocks, and collaborate with modeling teams to optimize performance, power, and area.

The role covers verification strategy, design features refinement, and integration at the SoC level, requiring deep expertise in Verilog/SystemVerilog and vector/matrix CPU engines.