Application Specific Integrated Circuit Design Engineer

Mirafra Technologies; Santa Clara (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Mirafra Technologies is seeking engineers to define and develop RISC-V CPU unit microarchitecture specifications, covering branch predictors, rename, instruction scheduling, vector execution, and load/store paths. The role includes RTL design quality, verification environment refinement, and PPA closure.

You will also leverage AI tools to accelerate CPU design and may mentor junior engineers based on seniority.

Qualifications

• Define and develop microarchitecture specifications for RISC-V CPU units.
• Responsible for RTL quality including design verification and PPA closure.
• Use AI tools to accelerate CPU design process.
• Mentor junior engineers as required.

Responsibilities

• Define and develop microarchitecture specifications for RISC-V CPU units.
• Responsible for RTL quality including design verification and PPA closure.
• Use AI tools to accelerate CPU design process.
• Mentor junior engineers as required.

Skills

Microarchitecture specifications

RTL Design

Verification

PPA closure

AI tools usage

Mentoring

Job description

RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure.

RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA.

AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process.

Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team.